Realistic fault analysis of CMOS analog building blocks

Abstract

High quality analog and mixed signal integrated circuits (ICs) require high quality testing. It is shown that test preparation, and test quality improvement of analog building blocks must be layout driven. For this, an IC defects-based analysis is used to study the impact of catastrophic faults on basic CMOS analog blocks. The impact on circuit behavior is analyzed for functional test and for i/sub DD/ power supply fault signatures. It is also demonstrated that a significant part of catastrophic faults cause out of specs performance, and may thus decrease the yield of the product, by an apparent parametric yield degradation. Finally, it is shown that layout level DFT (design for testability) can be rewardingly used to increase test confidence and product quality.