An interactive yield estimator as a VLSI CAD tool

Abstract

The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A/sub c/) which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A/sub c/ efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm to solve it efficiently. This algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed defect sensitivity map that can assist a physical designer in improving the yield of his/her layout.