芯片的平面布局会影响其成品率吗?

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595754

Z. Koren, I. Koren

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引用次数: 8

摘要

超大规模集成电路芯片的平面布局和预期良率通常被认为是完全不相关的问题。这种常用的假设并不一定适用于一些最近设计的集成了一些缺陷容限的VLSI芯片。这项工作的目的是研究平面规划和成品率之间的关系，为这类芯片。

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Does the floorplan of a chip affect its yield?

The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip.

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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