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Proceedings First Asian Test Symposium (ATS `92)最新文献

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Exhaustive two-pattern generation with cellular automata 元胞自动机穷举双模式生成
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224403
Sukumar Nandi, P. Chaudhuri, Swarup Roy, M. Sharma
{"title":"Exhaustive two-pattern generation with cellular automata","authors":"Sukumar Nandi, P. Chaudhuri, Swarup Roy, M. Sharma","doi":"10.1109/ATS.1992.224403","DOIUrl":"https://doi.org/10.1109/ATS.1992.224403","url":null,"abstract":"Two-patterns are required to test a transistor stuck-open fault or a delay fault within a combinational circuit. Cellular automata (CA) has been proposed as a two pattern generator. For a 2n-cell CA structure, the condition to generate all possible exhaustive two-pattern n-bits have been investigated. Criteria to select the most desirable CA structure have also been laid down.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"28 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132061133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A practical approach for the diagnosis of a MIMD network 一种实用的MIMD网络诊断方法
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224411
C. Aktouf, G. Mazaré, C. Robach, R. Velazco
{"title":"A practical approach for the diagnosis of a MIMD network","authors":"C. Aktouf, G. Mazaré, C. Robach, R. Velazco","doi":"10.1109/ATS.1992.224411","DOIUrl":"https://doi.org/10.1109/ATS.1992.224411","url":null,"abstract":"The authors present a self-diagnosis approach for validating a MIMD fine grain network. Based on a simple fault model, the authors propose an O(n/sup 2/) self diagnosis algorithm which is executed in a pipeline fashion. The functional test program of the processors together with simulation results are given.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114098539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Syndrome testable design software package, instrument and Syndrome testing system for sequential circuits 时序电路证候测试设计软件包、仪器及证候测试系统
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224405
Fanglei Wang, Jijie Wang
{"title":"Syndrome testable design software package, instrument and Syndrome testing system for sequential circuits","authors":"Fanglei Wang, Jijie Wang","doi":"10.1109/ATS.1992.224405","DOIUrl":"https://doi.org/10.1109/ATS.1992.224405","url":null,"abstract":"Syndrome testing and Syndrome design for testability are very difficult to put into practice. The authors propose some research results which can solve these difficulties. They include computer aid Syndrome testable design, Syndrome structured design for testability and multiple Syndrome testing instrument, etc. These techniques open the way for putting Syndrome testing and Syndrome design for testability into practice.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Functional tests for arbitration SRAM-type FIFOs 仲裁sram型fifo的功能测试
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224443
A. van de Goor, Y. Zorian
{"title":"Functional tests for arbitration SRAM-type FIFOs","authors":"A. van de Goor, Y. Zorian","doi":"10.1109/ATS.1992.224443","DOIUrl":"https://doi.org/10.1109/ATS.1992.224443","url":null,"abstract":"First-In-First-Out (FIFO) memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One way to implement a FIFO is to use a single-port SRAM memory with arbitration logic to resolve conflicts due to simultaneous read and write requests. The well-know functional tests for SRAMs (van de Goor, 1990 and 1991) cannot be applied to FIFOs because of their built in access restrictions. Functional fault models and functional tests for FIFOs are presented before, together with a set of tests and their correctness proofs for arbitration SRAM-type FIFOs.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132011820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Synthesis of autonomous TPG circuits oriented for two-pattern testing 面向双图测试的自主TPG电路的合成
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224402
K. Furuya, S. Seki, E. McCluskey
{"title":"Synthesis of autonomous TPG circuits oriented for two-pattern testing","authors":"K. Furuya, S. Seki, E. McCluskey","doi":"10.1109/ATS.1992.224402","DOIUrl":"https://doi.org/10.1109/ATS.1992.224402","url":null,"abstract":"A method to design one-dimensional cellular arrays for use as TPG circuits is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximal cycles are derived based on fast parallel implementations of LFSRs.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Highly efficient fault simulation exploiting hierarchy in circuit description 利用电路描述的层次性，高效的故障模拟
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224434
B.H. Seiss, H. Wittmann
{"title":"Highly efficient fault simulation exploiting hierarchy in circuit description","authors":"B.H. Seiss, H. Wittmann","doi":"10.1109/ATS.1992.224434","DOIUrl":"https://doi.org/10.1109/ATS.1992.224434","url":null,"abstract":"A highly efficient fault simulation approach is presented taking advantage of the hierarchy which can be found in most of todays circuit descriptions. Evident graphs are introduced to represent the structure of the hierarchy. Numerous experimental results for industrial circuits with up 90000 gates demonstrate the efficiency of the approach with respect to acceleration and reduction of the memory requirements as compared to an efficient gate level fault simulator.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic 使用规则时间逻辑的冗余系统比较器故障安全性的形式化验证
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224426
K. Kawakubo, H. Hiraishi
{"title":"Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic","authors":"K. Kawakubo, H. Hiraishi","doi":"10.1109/ATS.1992.224426","DOIUrl":"https://doi.org/10.1109/ATS.1992.224426","url":null,"abstract":"The authors propose a method of formal verification of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. The authors illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"21 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130803690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A complement-based fast algorithm to generate universal test sets for combinational function blocks 基于互补的组合功能块通用测试集快速生成算法
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224439
Beyin Chen, Chung-Len Lee
{"title":"A complement-based fast algorithm to generate universal test sets for combinational function blocks","authors":"Beyin Chen, Chung-Len Lee","doi":"10.1109/ATS.1992.224439","DOIUrl":"https://doi.org/10.1109/ATS.1992.224439","url":null,"abstract":"A fast algorithm to generate the universal test sets (UTS) for combinational function blocks is presented. The algorithm generates the UTS directly by Shannon-expanding and complementing the function, instead of the conventional truth table enumerating. This significantly reduces the time complexity and the memory requirements. Experimental results show that this algorithm achieves an improvement of 2 approximately 6 orders of magnitude in computational efficiency over that described by B. Sheldon and J.R. Akers (1973). This makes the UTS generation be practical for combinational function blocks.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Novel image-based LSI diagnostic method using E-beam without CAD database 一种基于图像的无CAD数据库电子束LSI诊断方法
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224414
T. Nakamura, Y. Hanagama, K. Nikawa, T. Tsujide, K. Morohashi, K. Kanai
{"title":"Novel image-based LSI diagnostic method using E-beam without CAD database","authors":"T. Nakamura, Y. Hanagama, K. Nikawa, T. Tsujide, K. Morohashi, K. Kanai","doi":"10.1109/ATS.1992.224414","DOIUrl":"https://doi.org/10.1109/ATS.1992.224414","url":null,"abstract":"Novel voltage contrast image-based methods have been developed concerning voltage contrast image acquisition using electron beam tester and concerning fault searching on a VLSI chip, and have been applied to real faults of passivated VLSI devices. The developed voltage contrast image acquisition methods have shorten the acquisition time about 1200 times faster than that of the conventional stroboscopic methods and have given better image quality that that of conventional method. The method employed continuous e-beam scanning and gated sampling image signal technique (CGFI) technique. The continuous e-beam scanning may prevent the fading voltage contrast and give good voltage contrast image. The method also employed test vector shortening technique, which has a merit in shortening testing time and avoiding wrong fault tracing back.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Localization and aftereffect of automatic test generation 自动测试生成的定位与后效
Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI: 10.1109/ATS.1992.224440
Zhongcheng Li, Yuqi Pan, Y. Min
{"title":"Localization and aftereffect of automatic test generation","authors":"Zhongcheng Li, Yuqi Pan, Y. Min","doi":"10.1109/ATS.1992.224440","DOIUrl":"https://doi.org/10.1109/ATS.1992.224440","url":null,"abstract":"Improvement on efficiency of test pattern generation (TPG) algorithms for large combinational circuits has long been a major concern. Two new concepts, localization and aftereffect, are introduced to enhance the efficiency. Based on the concepts, three techniques, partial implication, aftereffect of identified undetectable faults and shared sensitization, are adopted in a TPG system, SABATPG. Experiments for the 10 ISCAS benchmark circuits show that the computing time of SABATPG for test generation is 19.42% shorter than that of FAN algorithm.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"41 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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