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An ultra-low-voltage all-digital PLL for energy harvesting applications 用于能量收集应用的超低电压全数字锁相环
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942029
J. Silver, K. Sankaragomathi, B. Otis
{"title":"An ultra-low-voltage all-digital PLL for energy harvesting applications","authors":"J. Silver, K. Sankaragomathi, B. Otis","doi":"10.1109/ESSCIRC.2014.6942029","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942029","url":null,"abstract":"A 2 GHz all-digital phase locked loop (ADPLL) with core components operating from a 300-mV supply is presented. Ultra-low voltage frequency division and phase/frequency quantization are performed by a ring oscillator that is superharmonically injection-locked to the digitally-controlled oscillator (DCO). An injection-locking technique is proposed which facilitates locking with no additional active devices, minimizing capacitive loading and maximizing the oscillation frequency of the divider at low voltage. The ADPLL is fabricated in a 65-nm CMOS process, and consumes a total of 780 μW, 720μW from a 300-mV supply (VDDL) and 60μW from a 600-mV supply (VDDH).","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131038166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators 搭载矢量加速器的45nm 1.3GHz 16.7双精度GFLOPS/W RISC-V处理器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942056
Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, V. Stojanović, K. Asanović
{"title":"A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators","authors":"Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, V. Stojanović, K. Asanović","doi":"10.1109/ESSCIRC.2014.6942056","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942056","url":null,"abstract":"A 64-bit dual-core RISC-V processor with vector accelerators has been fabricated in a 45nm SOI process. This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley. In a standard 40nm process, the RISC-V scalar core scores 10% higher in DMIPS/MHz than the Cortex-A5, ARM's comparable single-issue in-order scalar core, and is 49% more area-efficient. To demonstrate the extensibility of the RISC-V ISA, we integrate a custom vector accelerator alongside each single-issue in-order scalar core. The vector accelerator is 1.8× more energy-efficient than the IBM Blue Gene/Q processor, and 2.6× more than the IBM Cell processor, both fabricated in the same process. The dual-core RISC-V processor achieves maximum clock frequency of 1.3GHz at 1.2V and peak energy efficiency of 16.7 double-precision GFLOPS/W at 0.65V with an area of 3mm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125531945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 128
An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC 一种基于比率-度量δ - σ ADC的涡流位移-数字转换器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942107
A. Fekri, M. R. Nabavi, N. Radeljic-Jakic, Z. Chang, M. Pertijs, S. Nihtianov
{"title":"An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC","authors":"A. Fekri, M. R. Nabavi, N. Radeljic-Jakic, Z. Chang, M. Pertijs, S. Nihtianov","doi":"10.1109/ESSCIRC.2014.6942107","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942107","url":null,"abstract":"This paper describes a smart Eddy-current displacement sensor for use in precision industrial applications. A novel readout scheme based on ratio-metric delta-sigma analog-to-digital conversion is proposed. The system employs two sensing coils incorporated in a low-power front-end oscillator. This produces two anti-phase outputs whose amplitudes are proportional to the inductances of the coils, and are thus a differential function of displacement. After synchronous down-conversion, these signals are fed into a second-order continuous-time delta-sigma modulator that directly produces a digital output that is a ratio-metric function of the coil inductances. This approach eliminates the need for a stable voltage reference, suppresses the oscillator's multiplicative noise contributions, and effectively filters the ripple associated with the down-conversion. The sensors are excited at 15 MHz, which reduces the eddy-current penetration depth to only a few tens of μm. The interface has been realized in a 0.35 μm BiCMOS technology and consumes 18 mW from a 3.3 V supply. In a measurement time of 1 ms, it digitizes the inductance ratio with a resolution of 15 bits, and thus achieves a displacement resolution of 135 nm on a range of 3 mm.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114497663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique 采用双向单面开关技术的24µW 11位1毫秒/秒SAR ADC
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942061
Long Chen, A. Sanyal, Ji Ma, Nan Sun
{"title":"A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique","authors":"Long Chen, A. Sanyal, Ji Ma, Nan Sun","doi":"10.1109/ESSCIRC.2014.6942061","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942061","url":null,"abstract":"This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic switching technique that also has only 1 switching event, the comparator input common-mode voltage for the proposed technique does not converge to ground but to Vcm, and thus, obviates the need for a specially designed comparator. To further reduce power, a segmented common-centroid capacitor layout is developed to ensure good matching accuracy. An 11-bit prototype ADC fabricated in 0.18-μm 1P6M CMOS technology achieves an ENOB of 10.3 bits and an SFDR of 77 dB. Operating at 1 MS/s, it consumes only 24 μW from a 1V power supply, leading to a FOM of 19.9 fJ/conv-step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117322246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems 用于电源管理系统中高效栅极驱动器的高压电荷存储自举电路
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942046
A. Seidel, M. Costa, J. Joos, B. Wicht
{"title":"Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems","authors":"A. Seidel, M. Costa, J. Joos, B. Wicht","doi":"10.1109/ESSCIRC.2014.6942046","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942046","url":null,"abstract":"Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129523498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip 28纳米移动片上系统的数字辅助模拟和模拟辅助数字设计技术
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942125
Xicheng Jiang, Narayan Prasad Ramachandran, D. Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang
{"title":"Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip","authors":"Xicheng Jiang, Narayan Prasad Ramachandran, D. Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang","doi":"10.1109/ESSCIRC.2014.6942125","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942125","url":null,"abstract":"A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 μm2/Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receivers 一个3khz闪烁噪声角，奇相有源混频器，用于直接转换接收器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942064
Dongju Lee, Minjae Lee
{"title":"A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receivers","authors":"Dongju Lee, Minjae Lee","doi":"10.1109/ESSCIRC.2014.6942064","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942064","url":null,"abstract":"We present a new type of flicker noise, mismatch up-converting active mixer with an odd number of cascode switching pairs that relax the local oscillator (LO) switching speed, which reduces the flicker noise from indirect mechanisms. The high-crossing master LO drivers improve the IIP3 at a 1.2 V supply voltage, and a frequency-reconfigurable LO generator is also presented for multiband operations. The measured flicker noise corner is <; 4 kHz with 13 dBm IIP3 and > 60 dBm IIP2 at the 1.8 GHz effective LO frequency.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132084493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensing 用于时间分辨荧光和拉曼传感的256 × 8 SPAD线传感器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942042
N. Krstajić, R. Walker, J. Levitt, S. Poland, Day-Uei Li, S. Ameer-Beg, R. Henderson
{"title":"A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensing","authors":"N. Krstajić, R. Walker, J. Levitt, S. Poland, Day-Uei Li, S. Ameer-Beg, R. Henderson","doi":"10.1109/ESSCIRC.2014.6942042","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942042","url":null,"abstract":"A 256 × 8 single photon avalanche diode (SPAD) time-resolved single photon counting (TCPSC) line sensor enables both fluorescence and Raman spectroscopy in a single device. The 23.78μm pitch, 46.8% fill-factor SPAD array is implemented in a 0.13μm CMOS image sensor process. Integrating time to digital converters (TDCs) implement on-chip mono-exponential fluorescence lifetime pre-calculation allowing timing of 65k photons/pixel at 500s-1 line rate at 40ps resolution using centre-of-mass method (CMM). TCSPC histograms may also be generated with 320ps bin resolution for multi-exponential analysis.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121054299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS 采用低噪声ADPLL、宽带PM/AM调制器和65纳米CMOS线性化PA的WCDMA/WLAN数字极极发射机
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942100
S. Zheng, H. Luong
{"title":"A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS","authors":"S. Zheng, H. Luong","doi":"10.1109/ESSCIRC.2014.6942100","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942100","url":null,"abstract":"A single-chip digital polar transmitter integrates an all-digital synthesizer, a PM/AM modulator, and a linearized power amplifier for WCDMA/WLAN. The 1.7~2.5GHz LO signal is generated from an ADPLL together with a ÷1.5 divider to eliminate DCO pulling. A 2-segment ΣΔ phase modulator enhances the PM bandwidth up to 200MHz, and a digital polar amplifier employs AM-replica linearization to eliminate predistortion. The TX measures EVM 4% for a 20MHz-bandwidth 64-QAM while providing a peak output power of 22.1dBm with bit-to-RF efficiency 27.6%.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A spectrum-equalizing analog front end for low-power electrocorticography recording 用于低功耗皮质电成像记录的频谱均衡模拟前端
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942033
W. A. Smith, Brian Mogen, E. Fetz, B. Otis
{"title":"A spectrum-equalizing analog front end for low-power electrocorticography recording","authors":"W. A. Smith, Brian Mogen, E. Fetz, B. Otis","doi":"10.1109/ESSCIRC.2014.6942033","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942033","url":null,"abstract":"Electrocorticography (ECoG) has spectral characteristics that allow for possible efficiency improvements over traditional broadband recording of low frequency (1-150 Hz) data. In this paper we propose a spectrum-equalization technique for ECoG recording that can potentially decrease the dynamic range requirements of digitization by more than two orders of magnitude, corresponding to more than 6 bits of ADC resolution. We additionally propose relaxed noise requirements for recording based on the signal spectrum and content. We demonstrate a fabricated analog front end and ADC in 65nm CMOS utilizing this equalization technique and with the proposed reduced noise requirements. This paper will show that the fabricated signal chain reproduces ECoG data with fidelity.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114835674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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