Xicheng Jiang, Narayan Prasad Ramachandran, D. Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang
{"title":"28纳米移动片上系统的数字辅助模拟和模拟辅助数字设计技术","authors":"Xicheng Jiang, Narayan Prasad Ramachandran, D. Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang","doi":"10.1109/ESSCIRC.2014.6942125","DOIUrl":null,"url":null,"abstract":"A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 μm2/Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip\",\"authors\":\"Xicheng Jiang, Narayan Prasad Ramachandran, D. Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang\",\"doi\":\"10.1109/ESSCIRC.2014.6942125\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 μm2/Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.\",\"PeriodicalId\":202377,\"journal\":{\"name\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2014.6942125\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942125","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip
A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 μm2/Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
