发布求助
文献互助 智能选刊 最新文献

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)最新文献

筛选
英文 中文
How chips helped discover the Higgs boson at CERN 芯片是如何帮助欧洲核子研究中心发现希格斯玻色子的
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948747
W. Snoeys
{"title":"How chips helped discover the Higgs boson at CERN","authors":"W. Snoeys","doi":"10.1109/ESSDERC.2014.6948747","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948747","url":null,"abstract":"Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in diameter, constructed around these interaction points to take pictures of collision products as they fly away from the collision point. They contain millions of channels, often implemented as reverse biased silicon pin diode arrays covering areas of up to 200 m2 in the center of the experiment, generating a small (~1fC) electric charge upon particle traversals. Integrated circuits provide the readout, and accept collision rates of about 40 MHz with on-line selection of potentially interesting events before data storage. Power consumption directly impacts the measurement quality as it governs the amount of material present in the detector. Radiation tolerance has to exceed space requirements by orders of magnitude. The presence of tens of thousands of chips in a single system requires special attention to uniformity, robustness and redundancy.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131479819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamforming 30/35GHz相控阵发射器前端，Psat >+14dBm, 10°相位/5位振幅分辨率，用于高级波束形成
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942049
Y. Pei, Ying Chen, D. Leenaerts, Bianca Slaats, A. Zamanifekri
{"title":"A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamforming","authors":"Y. Pei, Ying Chen, D. Leenaerts, Bianca Slaats, A. Zamanifekri","doi":"10.1109/ESSCIRC.2014.6942049","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942049","url":null,"abstract":"A 30/35 GHz dual-band phased array transmitter (TX) front-end is demonstrated in a 0.25um SiGe:C BiCMOS process. The front-end provides variable phase shifts from 0°~360° with a ~10° resolution. A 5-bit amplitude resolution is achieved for advanced beamforming algorithms. Accurate transmitted beam patterns can be generated by applying a genetic algorithm with the achieved phase and amplitude resolution. The front-end transmits a >+14dBm saturation output power with >+15dB gain and >+22dBm OIP3 at 30/35GHz.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125218264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 50 µW, 2.1 mdeg/s/√Hz frequency-to-digital converter for frequency-output MEMS gyroscopes 50µW, 2.1 mdeg/s/√Hz频率-数字转换器，用于频率输出MEMS陀螺仪
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942106
I. Izyumin, M. Kline, Y. Yeh, B. Eminoglu, B. Boser
{"title":"A 50 µW, 2.1 mdeg/s/√Hz frequency-to-digital converter for frequency-output MEMS gyroscopes","authors":"I. Izyumin, M. Kline, Y. Yeh, B. Eminoglu, B. Boser","doi":"10.1109/ESSCIRC.2014.6942106","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942106","url":null,"abstract":"Frequency-modulated operation of MEMS gyroscopes promises numerous benefits, including inherently accurate scale factor, improved bias stability, high dynamic range, and low power dissipation. An FM demodulator based on sigma-delta frequency-to-digital conversion decouples dynamic range from power dissipation to achieve a resolution of 41.1μHz in a 50 Hz bandwidth for a 30 kHz signal (2.1 mdeg/s/√Hz) with a maximum input range of 2000 deg/s while consuming 27.6μA at 1.8V. The high performance and low power consumption of this circuit enable the development of high performance, ultra-low-power, frequency-output gyroscopes and other frequency-output MEMS sensors.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125515114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology 基于130nm CMOS-SOI技术的低频段蜂窝终端天线阻抗调谐器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942121
J. Lindstrand, I. Vasilev, H. Sjöland
{"title":"A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology","authors":"J. Lindstrand, I. Vasilev, H. Sjöland","doi":"10.1109/ESSCIRC.2014.6942121","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942121","url":null,"abstract":"This paper presents a low band antenna impedance tuner in 130nm CMOS-SOI technology. It consists of three digitally controlled switched capacitor banks and two off-chip inductors and is intended for use in terminals supporting modern cellular standards like WCDMA and LTE. By using a negative gate bias in the off state, linearity can be improved and maintained. Measurements show an OIP3 exceeding +55dBm for all measured impedance states, which cover a VSWR of up to 5.4. The measured minimum loss is 1dB or lower in the frequency range from 700-900MHz with spurious emissions below -30dBm at +33dBm input power. The switched capacitors are implemented with eight stacked transistors to yield a voltage handling of at least 20V, and in order to handle the large voltages custom designed capacitors are used.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114945740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A DDR3/4 memory link TX supporting 24–40 Ω, 0.8–1.6 V, 0.8–5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI DDR3/4内存链路TX支持24-40 Ω， 0.8-1.6 V, 0.8-5.0 Gb/s，摆率控制和薄氧化物输出级，22nm CMOS SOI
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942040
M. Kossel, C. Menolfi, T. Toifl, P. Francese, M. Braendli, T. Morf, L. Kull, T. Andersen, Hazar Yueksel
{"title":"A DDR3/4 memory link TX supporting 24–40 Ω, 0.8–1.6 V, 0.8–5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI","authors":"M. Kossel, C. Menolfi, T. Toifl, P. Francese, M. Braendli, T. Morf, L. Kull, T. Andersen, Hazar Yueksel","doi":"10.1109/ESSCIRC.2014.6942040","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942040","url":null,"abstract":"A transmitter for data (DQ) lines in a DDR3/4 memory link is presented. The transmitter supports a drive impedance range of 24-40 Ω, operates from a 0.8-1.6 V supply range, and runs between 0.8 and 5.0 Gb/s. The DDR TX includes a clock-feathering-based slew rate control with duty cycle adjustment and uses thin oxide output stages for power saving. The power supply for the thin oxide pull-up protection is provided by an on-chip voltage regulator. Also FFE with 1 postcursor tap and max. 9.5 dB de-emphasis at 40 Ω is included. Results measured with typical DDR settings such as 30 Ω drive impedance and 1.35 V supply show a 1.2-5.8 V/ns slew rate range into a 50 Ω termination, an energy efficiency at 2133 Mb/s of 4.4 pJ/bit and TJ (BER 10-12) of 26 ps. The transmitter is fabricated in 22-nm CMOS SOI and has a size of 132 × 83 μm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter 一个使用DS调制器和零isi滤波器的2通道1MHz BW, 80.5 dB DR ADC
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942110
Debasish Behera, N. Krishnapura
{"title":"A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter","authors":"Debasish Behera, N. Krishnapura","doi":"10.1109/ESSCIRC.2014.6942110","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942110","url":null,"abstract":"It is shown that memoryless analog-to-digital conversion using ΔΣ modulators is possible without resetting the modulator or decimation filters by using a suitable signal transfer function for the modulator and a decimation filter which satisfies Nyquist intersymbol interference (ISI) criterion. This architecture enables memoryless operation over the entire signal bandwidth of the ΔΣ modulator which is significantly higher than the bandwidth in incremental ΔΣ architectures in which the modulator is reset. A two-channel ADC with a total effective sampling rate of fs/64 per channel is built using a third order 32× oversampled switched-capacitor ΔΣ modulator. The prototype in 0.18 μm CMOS occupies 2.1 mm2 and consumes 59.63mW. At 16MHz (64MHz) sampling rate for the DSM, the dynamic range (DR) of the standalone modulator is 86.5 dB(85.1 dB), and that in two-channel mode, with perchannel rate of 250 kHz (1MHz) is 81 dB (80.5 dB). The maximum SNR in multiplexed mode at 16MHz (64MHz) sampling rate is 80.3 dB(68.6 dB). At both sampling rates, the inter-channel crosstalk due to maximum input on the other channel is below 77.7 dB.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129652770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst 一种带频偏补偿的8gbps盲过采样CDR
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942117
Abhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, S. Chopra, Tapas Nandy, Vivek Uppal
{"title":"A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst","authors":"Abhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, S. Chopra, Tapas Nandy, Vivek Uppal","doi":"10.1109/ESSCIRC.2014.6942117","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942117","url":null,"abstract":"This paper presents a 8 Gbps high jitter tolerance (JTOL) corner-frequency hybrid CDR that employs blind oversampling phase detector in conjunction with digital proportional integral controller (PIC) for phase/frequency tracking with +/-4000ppm frequency offset compensation over infinite burst. Need of the elasticity buffer has been obviated by using a method of time-varying divider ratios in word-clock generation. Analytical treatment of the CDR dynamics and insight into its JTOL are also presented. Short lock time and tracking over infinite burst make this CDR reusable across applications requiring either burst or continuous mode support. The device exhibits a JTOL corner-frequency of 50MHz and total jitter tolerance floor of 0.52 UI peak-to-peak @ BER of 10-10 in 28nm CMOS technology with 1.0V supply.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133830910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS 采用65纳米CMOS双位面积优化标准单元的35 fJ/bit访问亚vt存储器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942067
O. Andersson, B. Mohammadi, P. Meinerzhagen, J. Rodrigues
{"title":"A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS","authors":"O. Andersson, B. Mohammadi, P. Meinerzhagen, J. Rodrigues","doi":"10.1109/ESSCIRC.2014.6942067","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942067","url":null,"abstract":"A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131093553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Dynamic range enhanced readout circuit for a capacitive touch screen panel with current subtraction technique 采用电流减法技术的电容式触摸屏面板动态范围增强读出电路
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942088
Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, F. Bien
{"title":"Dynamic range enhanced readout circuit for a capacitive touch screen panel with current subtraction technique","authors":"Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, F. Bien","doi":"10.1109/ESSCIRC.2014.6942088","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942088","url":null,"abstract":"A dynamic range enhanced readout circuit using current subtraction technique is presented for a capacitive touch screen panels. A low-voltage, analog front-end circuit using a high-voltage input signal is implemented. A high voltage (> 10 V) parallel pulse signal is used as the transmitter signal. The receiver system was designed with low voltage (<; 5 V). A current-subtraction circuit (CSC) with a current mirror and switches is proposed to improve the signal-to-noise ratio (SNR). SNR is improved by removing excessive current from the touch screen panel. High-voltage parallel signaling method is used to further enhance the dynamic range. Dynamic range was increased by a factor of four and reduced the feedback capacitance from 20 to 5 pF. The proposed IC was implemented in a TSMC 0.18-μm high-voltage CMOS process. The power consumption of the chip is 11.2 mW and the chip size is 2.5 mm × 2.5 mm.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128854112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensation 采用零补偿vco放大器的40MHz四阶有源ugb - rc滤波器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942096
Chun-Wei Hsu, P. Kinget
{"title":"A 40MHz 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensation","authors":"Chun-Wei Hsu, P. Kinget","doi":"10.1109/ESSCIRC.2014.6942096","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942096","url":null,"abstract":"This paper describes a 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensation. The VCO-based amplifier intrinsically has a huge DC gain without the associated stability penalties of conventional multi-stage amplifiers such as reducing unity-gain bandwidth or requiring large area by compensation schemes. By using the large gain of the amplifier, the filter achieves small area and good linearity performance for a signal bandwidth of 40MHz. The filter prototype in a 55nm CMOS process has an active area of 0.07mm2 and a power consumption of 7.8mW at 1.2V. The measured in-band IIP3 and out-of-band IIP3 are 27.3dBm and 22.5dBm respectively.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"584 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115672938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信