{"title":"A Class-D CMOS DCO with an on-chip LDO","authors":"Luca Fanori, T. Mattsson, P. Andreani","doi":"10.1109/ESSCIRC.2014.6942090","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942090","url":null,"abstract":"This paper presents the co-design of a class-D digitally-controlled oscillator (DCO) and a low-dropout voltage regulator (LDO) generating the supply voltage for the DCO. Despite the high intrinsic supply pushing of the class-D oscillator topology, the LDO noise has only a very marginal impact on the DCO phase noise. The class-D DCO and LDO have been integrated in a 65 nm CMOS process without any thick top metal layer. The oscillation frequency is tunable between 3.0 GHz and 4.3 GHz, for a tuning range of 36%, with a fine frequency step below 3kHz and a fine frequency range of 10 MHz (both measured at 3GHz). Drawing 9.0 mA from 0.4V (corresponding to an unregulated supply voltage of 0.6 V), the phase noise is -145.5 dBc/Hz at a 10 MHz offset from a 3.0GHz carrier. The resulting FoM is 189.5 dBc/Hz, and varies less than 1dB across the tuning range. The FoM increases to above 190 dBc/Hz when the regulated supply voltage is 0.5 V.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Choi, Inhee Lee, Taekwang Jang, D. Blaauw, D. Sylvester
{"title":"A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs","authors":"M. Choi, Inhee Lee, Taekwang Jang, D. Blaauw, D. Sylvester","doi":"10.1109/ESSCIRC.2014.6942036","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942036","url":null,"abstract":"This paper proposes a MOSFET-only, 20pA, 780ppm/°C current reference that consumes 23pW. The ultra-low power circuit exploits subthreshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows low supply voltage sensitivity of 0.58%/V and a load sensitivity of 0.25%/V.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116877779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abdelali El Amraoui, M. Bocquet, F. Barros, J. Portal, M. Charbonneau, S. Jacob, J. Bablet, M. Benwadih, V. Fischer, R. Coppard, R. Gwoziecky
{"title":"Printed complementary organic thin film transistors based decoder for ferroelectric memory","authors":"Abdelali El Amraoui, M. Bocquet, F. Barros, J. Portal, M. Charbonneau, S. Jacob, J. Bablet, M. Benwadih, V. Fischer, R. Coppard, R. Gwoziecky","doi":"10.1109/ESSCIRC.2014.6942034","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942034","url":null,"abstract":"This paper presents a decoder circuit manufactured in a printed complementary organic TFT technology on flexible substrate. Decoder architecture, simulation and experimental results are detailed. In order to comply with current printed electronic capability, a tree based decoding architecture is specifically implemented in order to provide robust functionality with a limited number of transistors. Two different output stages are implemented in order to drive active and passive ferroelectric memory. To drive active matrix, a buffer output stage is proposed, whereas a pass-gate based output stage, with customizable voltage, is used for passive matrix. Characterization results show that the decoder for both output stage options is functional for a wide range of voltage from 40V down to 5V, and for timing between 5ms and 100ms.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125910879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency","authors":"Avishek Biswas, Yildiz Sinangil, A. Chandrakasan","doi":"10.1109/ESSCIRC.2014.6942074","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942074","url":null,"abstract":"This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 μA to 500 μA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, H. Ishikuro
{"title":"A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing","authors":"Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, H. Ishikuro","doi":"10.1109/ESSCIRC.2014.6942103","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942103","url":null,"abstract":"A SAW-filter-less LTE transmitter based on 65-nm CMOS technology, incorporating a passive quadrature modulator (QMOD) with band-pass-filter (BPF) I/Q summing technique, was developed. The passive operation and the BPF I/Q summing technique, respectively, contribute to low noise performance and high input impedance seen from baseband signal, resulting in low receiver-band noise and high linearity of the transmitter. A transmitter using the QMOD exhibits both inspecification receiver-band noise (<;-156 dBc/Hz) and high output 3rd intercept point (OIP3 = 20.6 dBm).","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dini, M. Filippi, A. Romani, M. Tartagni, V. Bottarel, G. Ricotti
{"title":"A 40 nA/source energy harvesting power converter for multiple and heterogeneous sources","authors":"M. Dini, M. Filippi, A. Romani, M. Tartagni, V. Bottarel, G. Ricotti","doi":"10.1109/ESSCIRC.2014.6942071","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942071","url":null,"abstract":"This paper presents a fully autonomous integrated circuit for power conversion from multiple and heterogeneous energy harvesting transducers. Five input channel are dedicated to vibrational harvesting and exploiting multi-frequency operations. Additional four input channels are dedicated to manage DC sources. An independent MPPT is applied on each channel. A relevant feature of the design is the use of specific nano-power design techniques which reduce the converter quiescent consumption down to 40 nA/source and still keep energy conversion efficiency up to 82.8%. Only few external components are required: an external capacitor for energy storage, a single inductor and four capacitors for MPPT on DC sources.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130591536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.008-mm2 area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring","authors":"Ugur Sonmez, Rui Quan, F. Sebastiano, K. Makinwa","doi":"10.1109/ESSCIRC.2014.6942105","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942105","url":null,"abstract":"An array of temperature sensors based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensors achieve an inaccuracy of ±2.4 °C (3σ) from -40 to 125 °C with no trimming and ±0.65 °C (3σ) with a one temperature trim. Each sensor occupies 0.008 mm<sup>2</sup>, and achieves a resolution of 0.21 °C (rms) at 1 kSa/s. This combination of accuracy, speed, and small size makes such sensors well suited for thermal monitoring in microprocessors and other systems-on-chip.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A semiconductor memory development and manufacturing perspective","authors":"G. Atwood, S. DeBoer, K. Prall, Linda Somerville","doi":"10.1109/ESSCIRC.2014.6942002","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942002","url":null,"abstract":"Semiconductor memories are growing in importance as they are now fundamental in every electronic system and offer new manufacturing and development challenges and opportunities. From a manufacturing point of view, the industry has undergone consolidation and today very few players are able to supply the high wafer volumes required by the global market. From a technology development point of view, new applications requiring lower power, higher memory density and improved performance creates opportunities for alternative memory technologies. Moreover, the shift to 3-dimensional integration and to new system architectures result in both manufacturing and technology challenges.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"149 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131991519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 13.56/402 MHz autonomous wireless sensor node with −18.2 dBm sensitivity and temperature monitoring in 0.18 /im CMOS","authors":"A. Mansano, S. Bagga, W. Serdijn","doi":"10.1109/ESSCIRC.2014.6942076","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942076","url":null,"abstract":"A multi-band autonomous wireless sensor node (AWSN) with temperature monitoring is designed in a standard 0.18 μm CMOS technology. The AWSN comprises a high efficiency energy harvester, a power management module, a temperature-to-time converter (TTC) and a passive 402-MHz MICS band OOK transmitter for backscattering transmission. The AWSN demonstrates a sensitivity of -18.2 dBm at 13.56 MHz. The energy harvester achieves an RF-to-DC power conversion efficiency (PCE) of 11.5 %. From 0 to 100 °C, the temperature conversion and temperature accuracy of the TTC are 1.5 μs/°C and 0.21 °C, respectively. The active area of the AWSN is 0.72 mm2. It consumes 1.5 μW (RMS).","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116677105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An E-Band low-noise Transformer-Coupled Quadrature VCO in 40 nm CMOS","authors":"M. Vigilante, P. Reynaert","doi":"10.1109/ESSCIRC.2014.6942112","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942112","url":null,"abstract":"This paper presents a Transformer-Coupled Quadrature VCO (TC-QVCO) designed to achieve low-noise performance at millimeter-wave. The VCO core is implemented combining the tuned-input tuned-output (TITO) oscillator and the Colpitts oscillator, while the coupling is realized by means of transformers, resulting in low noise and accurate quadrature phases. Designed in a 40 nm CMOS process, the TC-QVCO operates between 83.7 GHz and 88.7 GHz (i.e, 5.8% tuning range). Dissipating 28.4 mW from a 0.7 V supply, the measured phase noise is -118.8 dBc/Hz at 10 MHz offset from a 88.7 GHz carrier, resulting in a peak phase-noise FoM of -183.2 dBc/Hz. The I/Q phase error is less than 1.2° over the whole tuning range.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}