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A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopy 基于tdc的4×128时间门控拉曼光谱CMOS SPAD阵列
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942041
I. Nissinen, J. Nissinen, Jouni Holma, J. Kostamovaara
{"title":"A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopy","authors":"I. Nissinen, J. Nissinen, Jouni Holma, J. Kostamovaara","doi":"10.1109/ESSCIRC.2014.6942041","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942041","url":null,"abstract":"A 4×128 CMOS SPAD array has been designed and tested for a time-gated Raman spectroscopy. The SPAD array includes a 3-bit TDC for each of the SPAD elements (512). The TDC is designed to have 78 ps resolution in the first four bins for the accurate time position measurement of the Raman photons. The resolution is degraded for the last four bins used for fluorescence and background correction to achieve larger dynamic range. The timing skew of the bins of the TDC along spectral axis was measured to be ± 70 ps with 7 ps variation (sigma) in the bin widths.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124450394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A resistor-based temperature sensor for a real time clock with ±2ppm frequency stability 一种基于电阻的温度传感器，用于频率稳定性为±2ppm的实时时钟
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942104
Pyoungwon Park, K. Makinwa, D. Ruffieux
{"title":"A resistor-based temperature sensor for a real time clock with ±2ppm frequency stability","authors":"Pyoungwon Park, K. Makinwa, D. Ruffieux","doi":"10.1109/ESSCIRC.2014.6942104","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942104","url":null,"abstract":"A temperature sensor based on the temperature-dependence of integrated poly-silicon resistors is used to stabilize the quartz-crystal of a 131kHz real-time clock (RTC). After a 3-point calibration, the sensor achieves an inaccuracy of less than ±0.12°C (min-max) from -40°C to 85°C, which translates into a frequency stability of less than ±2ppm. The sensor also achieves 2.8mK (rms) resolution in a 32ms conversion time, which corresponds to a state-of-the-art resolution FOM of 8pJK2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter 一个33 mhz 70db信噪比的超源跟踪器低通模拟滤波器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942097
M. Matteis, A. Pezzotta, S. D’Amico, A. Baschirotto
{"title":"A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter","authors":"M. Matteis, A. Pezzotta, S. D’Amico, A. Baschirotto","doi":"10.1109/ESSCIRC.2014.6942097","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942097","url":null,"abstract":"In this paper a 4th-order low-pass continuous-time analog filter is presented. A smart and compact biquadratic cell has been realized using the super-source-follower circuit. The biquadratic cell synthesizes a 2nd-order low-pass transfer function, using only two capacitors and four transistors per stage: two transistors for gm-C transfer function and two transistors as current sources for biasing purpose. A 4th-order filter prototype has been integrated in CMOS 0.18μm technological node. The achieved Signal-to-Noise-Ratio is 70dB, with 8nV/√Hz in-band input referred noise. In-Band IIP3 is 18dBm. The current consumption for the entire 4th-order filter is 770μA, from a single 1.8V supply voltage.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132628385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS 一个1.2V 20dbm 60ghz功率放大器，增益32.4 dB，峰值PAE为20%，采用65nm CMOS
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942050
A. Larie, E. Kerhervé, B. Martineau, V. Knopik, D. Belot
{"title":"A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS","authors":"A. Larie, E. Kerhervé, B. Martineau, V. Knopik, D. Belot","doi":"10.1109/ESSCIRC.2014.6942050","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942050","url":null,"abstract":"A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the author's knowledge, this amplifier presents the highest figure of merit (FoM ITRS) among 60 GHz PAs using silicon technology.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134125654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS 采用65nm CMOS，基于TSPC逻辑的1V 2mW 17GHz多模分频器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942114
M. Krishna, Anil Jain, N. A. Quadir, P. Townsend, P. Ossieur
{"title":"A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS","authors":"M. Krishna, Anil Jain, N. A. Quadir, P. Townsend, P. Ossieur","doi":"10.1109/ESSCIRC.2014.6942114","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942114","url":null,"abstract":"We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50μm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134422813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS 一个20Mb/s, 2.76 pJ/b的UWB脉冲无线电TX，效率为11.7%，采用130 nm CMOS
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942078
F. Padovan, A. Bevilacqua, A. Neviani
{"title":"A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS","authors":"F. Padovan, A. Bevilacqua, A. Neviani","doi":"10.1109/ESSCIRC.2014.6942078","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942078","url":null,"abstract":"An UWB impulse radio transmitter for ultra-low energy neural recording applications is proposed. The transmitter is designed for robust and efficient operation in the 7.25-8.5GHz band, supporting communication ranges in excess to 4m. Powered by a low-voltage 0.5V supply, prototypes in a 130 nm CMOS technology are able to transmit 2.76 pJ/b PPM-modulated pulses to the antenna at a 20Mb/s data rate with an outstanding 11.7% overall energy efficiency.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117265861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS 180nm CMOS可编程增益1.8GHz三阶低通滤波器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942095
S. Abbasi, A. Shabra
{"title":"1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS","authors":"S. Abbasi, A. Shabra","doi":"10.1109/ESSCIRC.2014.6942095","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942095","url":null,"abstract":"A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123891012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 131.5GHz, −84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS 基于零移相耦合振荡器网络的131.5GHz - 84dBm灵敏度超再生接收机
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942053
Shunli Ma, Hao Yu, Y. Shang, W. M. Lim, Junyan Ren
{"title":"A 131.5GHz, −84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS","authors":"Shunli Ma, Hao Yu, Y. Shang, W. M. Lim, Junyan Ren","doi":"10.1109/ESSCIRC.2014.6942053","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942053","url":null,"abstract":"A CMOS high-sensitivity super-regenerative receiver is proposed for millimeter-wave imaging systems. With quench-control signals, two LC-tank oscillators are coupled in-phase by zero-phase-shifter network in a positive feedback loop. This leads to a high oscillatory amplification and improves the detection sensitivity. The circuit is realized in 65nm CMOS with a core area of 0.06 mm2. Measurements show that the receiver features a sensitivity of -84dBm, a noise-equivalent-power of 0.615fW/Hz0.5, a noise-figure of 7.26 dB and a power consumption of 8.1mW.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS 基于45nm CMOS的29.5 dBm e类失相射频功率放大器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942123
A. Banerjee, R. Hezar, Lei Ding, N. Schemm, B. Haroun
{"title":"A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS","authors":"A. Banerjee, R. Hezar, Lei Ding, N. Schemm, B. Haroun","doi":"10.1109/ESSCIRC.2014.6942123","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942123","url":null,"abstract":"A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS technology. Simulation results and measurement data are presented to demonstrate the performance of the proposed PA. The PA delivers 29.5 dBm peak output power at 2.4GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off and 21.16% drain efficiency at 6 dB power back-off. Better than -50 dBc ACPR is obtained with 64-QAM LTE signal with 10MHz and 20MHz bandwidth. 21% average efficiency is obtained with LTE signal with 6 dB peak-to-average power ratio (PAPR).","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128122165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC 11b900ms /s时间交错子测距流水线sar ADC
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942059
Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins
{"title":"An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC","authors":"Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins","doi":"10.1109/ESSCIRC.2014.6942059","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942059","url":null,"abstract":"This paper presents a sub-ranging 6-way time-interleaved pipelined-SAR ADC that achieves 900MS/s and 9.3 ENOB in 65nm CMOS. The architecture optimization is based on a pipelined-SAR structure that obtains high-speed with an optimized number of channels, thus leading to relaxed calibration with higher efficiency in power and area consumption. The proposed channel-selection-embedded bootstrap performs sampling instants synchronization without additional components, thus effectively suppressing the spurs from time skews below -65 dBFS. The mismatch errors due to offset and gain are all solved on-chip, whose spurs are suppressed below -67 dBFS. The prototype achieves 66 dB SFDR and 51.5 dB SNDR with a Nyquist input exhibiting a FoM of 56 fJ/conv.step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129127780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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