基于tdc的4×128时间门控拉曼光谱CMOS SPAD阵列

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI:10.1109/ESSCIRC.2014.6942041

I. Nissinen, J. Nissinen, Jouni Holma, J. Kostamovaara

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引用次数: 8

摘要

设计了一个4×128 CMOS SPAD阵列，并对其进行了时间门控拉曼光谱测试。SPAD阵列包括每个SPAD元素的3位TDC(512)。TDC设计为在前四个箱中具有78 ps的分辨率，用于精确测量拉曼光子的时间位置。分辨率降低的最后四个箱用于荧光和背景校正，以实现更大的动态范围。测得TDC箱体沿光谱轴的定时偏差为±70 ps，箱体宽度变化7 ps (sigma)。

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A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopy

A 4×128 CMOS SPAD array has been designed and tested for a time-gated Raman spectroscopy. The SPAD array includes a 3-bit TDC for each of the SPAD elements (512). The TDC is designed to have 78 ps resolution in the first four bins for the accurate time position measurement of the Raman photons. The resolution is degraded for the last four bins used for fluorescence and background correction to achieve larger dynamic range. The timing skew of the bins of the TDC along spectral axis was measured to be ± 70 ps with 7 ps variation (sigma) in the bin widths.

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ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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