{"title":"180nm CMOS可编程增益1.8GHz三阶低通滤波器","authors":"S. Abbasi, A. Shabra","doi":"10.1109/ESSCIRC.2014.6942095","DOIUrl":null,"url":null,"abstract":"A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS\",\"authors\":\"S. Abbasi, A. Shabra\",\"doi\":\"10.1109/ESSCIRC.2014.6942095\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.\",\"PeriodicalId\":202377,\"journal\":{\"name\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2014.6942095\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS
A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.
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