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Emerging analog-to-digital converters 新兴的模数转换器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942019
N. Maghari, U. Moon
{"title":"Emerging analog-to-digital converters","authors":"N. Maghari, U. Moon","doi":"10.1109/ESSCIRC.2014.6942019","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942019","url":null,"abstract":"Many analog IC designers and students are naturally drawn to ADCs. While some ADC realizations have had a lasting impact including pipelined ADCs with digital redundancy, flash ADCs with folding and interpolation, and multi-bit delta-sigma modulators with dynamic element matching, there are many more recent and emerging ADC design techniques that are receiving much attention and also gaining momentum in some areas. Many of these ideas are showered with doubts and honest criticism. However, we may also be entering a new era where a few of these developments could help resolve the tough submicron scaling challenge that analog designers face today. This paper will summarize and ponder the impact of a few selective as well as random slices of these emerging ADC designs.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128496097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C 79GHz可变增益低噪声放大器和28nm CMOS功率放大器，工作温度高达125°C
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942052
Alaa Medra, V. Giannini, D. Guermandi, P. Wambacq
{"title":"A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C","authors":"Alaa Medra, V. Giannini, D. Guermandi, P. Wambacq","doi":"10.1109/ESSCIRC.2014.6942052","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942052","url":null,"abstract":"This paper presents a 79GHz variable gain low-noise amplifier (LNA) and power amplifier (PA), both implemented in 28nm CMOS, and measured at temperatures from 27°C to 125°C. The 4-gain steps LNA and the 17dB gain PA are based on a multistage common source neutralized push-pull topology. The LNA achieves a gain of 23.8dB and a noise figure (NF) of 4.9dB, and the PA achieves a maximum power added efficiency (PAE) of 13.8% and a saturated output power (Psat) of 12.3dBm. At 125°C both the LNA and the PA are functional with NF <; 7dB and Psat >11dBm. This paper demonstrates the feasibility of using scaled CMOS technology (28nm) for automotive radars.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133657455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A 13b SAR ADC with eye-opening VCO based comparator 一个13b SAR ADC，带有令人大开眼界的VCO比较器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942109
K. Yoshioka, H. Ishikuro
{"title":"A 13b SAR ADC with eye-opening VCO based comparator","authors":"K. Yoshioka, H. Ishikuro","doi":"10.1109/ESSCIRC.2014.6942109","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942109","url":null,"abstract":"A low-power and high accuracy comparator based on voltage controlled ring-oscillator (VCO) is presented. By using the dead zone of phase detector effectively, the VCO comparator automatically changes its noise level depending on the input voltage level (Δvin). When Δvin is large, the comparator operates as a low-power delay-line based comparator. On the other hand, when Δvin is small, the VCO is enabled and eye is opened during the oscillation. This suppress input referred noise and enables accurate conversion. The number of oscillation cycle for one comparison is inversely proportional to Δvin and adaptive noise reduction is realized. The VCO comparator does not require any sort of tuning. A 13b SAR ADC with proposed VCO based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves SNDR 66 dB at 1 MS/s with FoM of 29fJ/conv.-step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133292689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation 一种新颖的超低相位噪声、可编程倍频器结构。应用于60ghz频率的产生
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942113
C. Jany, A. Siligaris, J. L. Jiménez, C. Bernier, P. Vincent, P. Ferrari
{"title":"A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation","authors":"C. Jany, A. Siligaris, J. L. Jiménez, C. Bernier, P. Vincent, P. Ferrari","doi":"10.1109/ESSCIRC.2014.6942113","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942113","url":null,"abstract":"This paper presents an original mmW frequency multiplier that provides a 58.32 GHz to 62.64 GHz LO starting from a much lower and fixed frequency of 2.16 GHz. It is composed of a pulsed VCO, which generates equally spaced harmonics in the 60 GHz band, and an injection locked oscillator (ILO) that selects the harmonic of interest. The CMOS 40nm circuit consumes 32 mW and occupies only 0.07 mm2. This novel programmable multiplication technique requires a unique fixed low frequency reference to perform multi-channel mmW LO generation. The phase noise of the output LO signal is only limited by the input low frequency reference phase noise and the frequency ratio between output and input signals. Thus, a 60 GHz signal has been generated with this technique with a record phase noise of -104 dBc/Hz @ 1MHz offset.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS 一个10位，550fs步进数字时间转换器在28nm CMOS
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942026
N. Markulić, K. Raczkowski, P. Wambacq, J. Craninckx
{"title":"A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS","authors":"N. Markulić, K. Raczkowski, P. Wambacq, J. Craninckx","doi":"10.1109/ESSCIRC.2014.6942026","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942026","url":null,"abstract":"This paper presents a 10-bit, 550-fs step Digital-to-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are below 1.8 LSB and 0.8 LSB, respectively. The DTC phase noise floor is below -154 dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At 10 GHz output, the in-band phase noise of the PLL with the DTC embedded is -105 dBc/Hz. The PLL achieves 270 fs RMS jitter, consuming 26 mW.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129070275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
A fast response integrated current-sensing circuit for peak-current-mode buck regulator 一种用于峰值电流型降压稳压器的快速响应集成电流传感电路
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942045
Jung-Woo Ha, B. Kong, J. Chun, Byeong-ha Park
{"title":"A fast response integrated current-sensing circuit for peak-current-mode buck regulator","authors":"Jung-Woo Ha, B. Kong, J. Chun, Byeong-ha Park","doi":"10.1109/ESSCIRC.2014.6942045","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942045","url":null,"abstract":"An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123325020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os 一个3.5pJ/bit 8分路前馈8分路判断反馈数字均衡器，用于16Gb/s I/ o
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942120
T. Toifl, P. Buchmann, T. Beukema, Michael P. Beakes, M. Braendli, P. Francese, C. Menolfi, M. Kossel, L. Kull, T. Morf
{"title":"A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os","authors":"T. Toifl, P. Buchmann, T. Beukema, Michael P. Beakes, M. Braendli, P. Francese, C. Menolfi, M. Kossel, L. Kull, T. Morf","doi":"10.1109/ESSCIRC.2014.6942120","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942120","url":null,"abstract":"In this paper, we present a digital equalizer for 16Gb/s backplane I/Os which consumes only 3.5pJ/bit for an 8-tap FFE and 4+4 tap DFE operation. Several design choices were chosen to enable low power consumption at high speed. First, the FFE leverages parallelism to lower the supply voltage, while the DFE runs from a higher supply to close the feedback loop. Second, the FFE uses distributed arithmetic to reduce the number of required additions. Third, the DFE taps leave a window of four equalizer taps, which are covered by the FFE, in order to close the timing. Finally, a custom digital design style was chosen, which enabled the optimization of critical blocks and wires. At 0.6V supply, the FFE was measured to consume 1pJ/bit, while the DFE consumes 1.6pJ/bit at 0.9V while running at 16Gb/s.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116721982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A pulse-driven LC-VCO with a figure-of-merit of −192dBc/Hz 脉冲驱动LC-VCO，品质因数为- 192dBc/Hz
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942092
A. Narayanan, K. Kimura, W. Deng, K. Okada, A. Matsuzawa
{"title":"A pulse-driven LC-VCO with a figure-of-merit of −192dBc/Hz","authors":"A. Narayanan, K. Kimura, W. Deng, K. Okada, A. Matsuzawa","doi":"10.1109/ESSCIRC.2014.6942092","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942092","url":null,"abstract":"This paper proposes a LC-VCO with a pulse-driven cross-coupled pair. The proposed pulse driving technique has the ability to achieve class-C like current waveform while reducing the Amplitude-Modulation to Phase-Modulation (A-PM) conversion by parasitic capacitance of the active devices. A VCO is implemented using the proposed technique in a standard 0.18um CMOS technology. It oscillates at a carrier frequency of 3.6GHz with a 0.65-V supply. The measured phase noise is -124 dBc/Hz @ 1MHz-offset with a power consumption of 2.05mW. The figure-of-merit (FoM) is -192 dBc/Hz.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129092032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e− rms, 19 e− rms offset spread and 3% rms gain spread 23552通道集成电路用于75µm间距的单光子计数像素探测器，ENC为89 e−rms，偏移扩展为19 e−rms，增益扩展为3% rms
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942043
P. Maj, P. Grybos, P. Kmon, R. Szczygiel
{"title":"23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e− rms, 19 e− rms offset spread and 3% rms gain spread","authors":"P. Maj, P. Grybos, P. Kmon, R. Szczygiel","doi":"10.1109/ESSCIRC.2014.6942043","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942043","url":null,"abstract":"We report on the novel method of an in-pixel offset and gain correction for implementation in multichannel hybrid detector readout circuits. A prototype ASIC consisting of 23552 square shaped pixels of 75 μm pitch was designed and fabricated in CMOS 130 nm technology. Each pixel containing charge sensitive amplifier, shaper, discriminator, correction circuits and two 14-bit counters has an equivalent noise charge of 89 e- rms and dissipates only 25 μW. Tests prove its exceptional uniformity with an offset spread of 19e- rms and the gain spread of only 3%, rms what is good enough for color X-Ray imaging. The paper presents the architecture of the ASIC, a transistor level novel schematic of key blocks used for offset and gain trimming, the testing procedure and its results.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 2.45GHz, 50uW wake-up receiver front-end with −88dBm sensitivity and 250kbps data rate 2.45GHz, 50uW唤醒接收器前端，灵敏度- 88dBm，数据速率250kbps
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942065
C. Bryant, H. Sjöland
{"title":"A 2.45GHz, 50uW wake-up receiver front-end with −88dBm sensitivity and 250kbps data rate","authors":"C. Bryant, H. Sjöland","doi":"10.1109/ESSCIRC.2014.6942065","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942065","url":null,"abstract":"This paper presents a 2.45 GHz wake-up receiver front-end intended for use in sensor networks, and is designed to receive data modulated with on-off-keying. Manufactured in 65 nm CMOS it employs an uncertain IF structure with three-phase passive mixer and high gain amplifier chain. With the modulation frequency response tailored to the detector behavior, it achieves a sensitivity of -88 dBm at BER of 10-3 with a data rate of 250kbps. Operating on a 0.75V supply it has a power consumption of just 50μW. It provides a 50 Ω input match completely on-chip using a compact inductor and has an active area of just 0.07mm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126937898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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