A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

Abstract

This paper presents a 10-bit, 550-fs step Digital-to-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are below 1.8 LSB and 0.8 LSB, respectively. The DTC phase noise floor is below -154 dBc/Hz at 0.5 mW power consumption from a 0.9 V supply. At 10 GHz output, the in-band phase noise of the PLL with the DTC embedded is -105 dBc/Hz. The PLL achieves 270 fs RMS jitter, consuming 26 mW.