A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation

Abstract

This paper presents an original mmW frequency multiplier that provides a 58.32 GHz to 62.64 GHz LO starting from a much lower and fixed frequency of 2.16 GHz. It is composed of a pulsed VCO, which generates equally spaced harmonics in the 60 GHz band, and an injection locked oscillator (ILO) that selects the harmonic of interest. The CMOS 40nm circuit consumes 32 mW and occupies only 0.07 mm2. This novel programmable multiplication technique requires a unique fixed low frequency reference to perform multi-channel mmW LO generation. The phase noise of the output LO signal is only limited by the input low frequency reference phase noise and the frequency ratio between output and input signals. Thus, a 60 GHz signal has been generated with this technique with a record phase noise of -104 dBc/Hz @ 1MHz offset.