1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS

Abstract

A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.