{"title":"A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency","authors":"Avishek Biswas, Yildiz Sinangil, A. Chandrakasan","doi":"10.1109/ESSCIRC.2014.6942074","DOIUrl":null,"url":null,"abstract":"This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 μA to 500 μA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942074","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottom-plate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 μA to 500 μA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.