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Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS 时间交错C-2C SAR ADC与背景时序偏差校准在65nm CMOS
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942058
Luke Wang, Qiwei Wang, A. C. Carusone
{"title":"Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS","authors":"Luke Wang, Qiwei Wang, A. C. Carusone","doi":"10.1109/ESSCIRC.2014.6942058","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942058","url":null,"abstract":"This paper presents a 5GS/s 8-bit 40-way time-interleaved SAR ADC fabricated in 65nm CMOS. Two-level hierarchical interleaving is employed, resulting in 4 sub-ADCs each operating at 1.25GS/s at the topmost level with front-end track and hold samplers. The sub-ADCs use capacitive C-2C DACs to minimize the input capacitance and area. A novel background timing skew calibration method is used which requires no redundant signal paths. After calibration, the ADC achieves an SNDR of 33.3dB at Nyquist and consumes 138.6mW from a 1V supply with a 5GS/s sampling rate, yielding an FOM of 738fJ/conv-step. The individual sub-ADC achieves an SNDR of 37.9dB at Nyquist and consumes 34.2mW, yielding an FOM of 428fJ/conv-step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Blocker tolerant software defined receivers 拦截容忍软件定义的接收器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942018
H. Darabi, D. Murphy, M. Mikhemar, A. Mirzaei
{"title":"Blocker tolerant software defined receivers","authors":"H. Darabi, D. Murphy, M. Mikhemar, A. Mirzaei","doi":"10.1109/ESSCIRC.2014.6942018","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942018","url":null,"abstract":"Various receiver architectures suitable for SDR and cognitive applications are proposed. To break the traditional noise-linearity-matching trade-off, we offer alternative topologies that are capable of tolerating large blockers without compromising the noise figure. The issues of harmonic rejection and reciprocal mixing are addressed as well and appropriate receiver architectures are highlighted. Case studies for various applications are presented describing the design details and pros and cons of each.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope tracking 具有包络跟踪功能的多频段Rel9 WCDMA/HSDPA/TDD LTE和FDD LTE收发器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942102
S. Tadjpour, P. Rossi, L. Romanò, R. Chokkalingam, H. Firouzkouhi, Feng Shi, M. Leroux, D. Gerna, A. Venca, J. Vasa, B. Ramachandran, B. Brunn, A. Pirola, D. Ottini, A. Milani, E. Sacchi, M. Behera, X. Chen, U. Decanis, Marika Tedeschi, S. DalToso, W. Eyssa, C. Cakir, C. Prakash, Yong He, N. Damavandi, R. Srinivasan, D. Shum, X. Fan, C. Yu, Engin Pehlivanoglu, H. Zarei, A. Loke, G. Uehara, R. Castello, Y. Song
{"title":"A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope tracking","authors":"S. Tadjpour, P. Rossi, L. Romanò, R. Chokkalingam, H. Firouzkouhi, Feng Shi, M. Leroux, D. Gerna, A. Venca, J. Vasa, B. Ramachandran, B. Brunn, A. Pirola, D. Ottini, A. Milani, E. Sacchi, M. Behera, X. Chen, U. Decanis, Marika Tedeschi, S. DalToso, W. Eyssa, C. Cakir, C. Prakash, Yong He, N. Damavandi, R. Srinivasan, D. Shum, X. Fan, C. Yu, Engin Pehlivanoglu, H. Zarei, A. Loke, G. Uehara, R. Castello, Y. Song","doi":"10.1109/ESSCIRC.2014.6942102","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942102","url":null,"abstract":"This paper presents a transceiver capable of supporting 2G/3G/4G LTE FDD bands 1-20 and TDD bands 34-41. The chip includes main and diversity receivers, direct conversion transmitter, internal closed loop power control, antenna tuning and Envelope Tracking DAC. It supports Rel 9 dual band dual carrier HSDPA using a second Receive PLL. The Receiver has better than 2.5dB Noise Figure and better than 50dBm IIP2 for all modes. The transmitter uses class AB power mixer for better power consumption. The overall chip is fabricated in TSMC 55nm process and occupies 19mm2 of area and consumes 92mA from the battery at 0dBm transmit power.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130076562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An improved low-power CMOS thyristor-based micro-to-millisecond delay element 一种改进的低功耗CMOS晶闸管微毫秒延时元件
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942037
B. Saft, Eric Schaefer, A. Jager, Alexander Rolapp, E. Hennig
{"title":"An improved low-power CMOS thyristor-based micro-to-millisecond delay element","authors":"B. Saft, Eric Schaefer, A. Jager, Alexander Rolapp, E. Hennig","doi":"10.1109/ESSCIRC.2014.6942037","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942037","url":null,"abstract":"We present a novel low-power CMOS thyristor-based delay element for delay durations in the micro- to millisecond ranges. Starting from a basic CMOS thyristor delay circuit, we propose several modifications to reduce the energy/delay ratio by a factor of four: The threshold voltage of the internal CMOS thyristor is raised and a pull-up/down current source is used to increase the delay duration and reduce the influence of subthreshold leakage current on integration time and nonlinearity. A second CMOS thyristor stage increases the steepness of the transition slopes, thereby reducing shunt currents in subsequent stages during the switching event. The circuit was designed and fabricated in a commercial 0.35-μm CMOS process. Measurements were performed on a ring oscillator comprising three instances of the proposed delay element. By varying the bias currents of the elements, the delay duration can be tuned over more than three decades from 4 μs to 22 ms with excellent linearity.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125674916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization 40nm CMOS的60GHz发射机，实现mm精度的离散载波定位
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942079
P. Indirayanti, Tuba Ayhan, M. Verhelst, W. Dehaene, P. Reynaert
{"title":"A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization","authors":"P. Indirayanti, Tuba Ayhan, M. Verhelst, W. Dehaene, P. Reynaert","doi":"10.1109/ESSCIRC.2014.6942079","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942079","url":null,"abstract":"This paper presents an efficient multicarrier 60GHz transmitter for distance measurement (ranging) in an indoor wireless localization system. By exploiting hardware-algorithm co-design, a high precision, high update rate, yet power efficient transmitter architecture is achieved, which comprises subcarrier generation through frequency division, an upconverter, and a power amplifier. An efficient frequency generation through digital design is ensured by means of co-design with the amplitude nonlinearity-tolerant algorithm. In consequence, conventional power hungry baseband blocks, such as DAC and OFDM processor, are avoided. Moreover, symbol selection is performed to minimize PAPR. The transmitter achieves 0.7-2.4mm precision demonstrated over a distance of 4m. During operation, the core digital subcarrier generator generates 16 non-equidistant subcarriers, while consuming an average power of 1.8mW out of 0.9V supply with an input clock of 3GHz. The upconverter and the power amplifier altogether consume around 127mW. The total active area of the core transmitter circuit is 0.9mm2. The chip is fabricated in a 40nm general purpose CMOS process.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"52 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130651339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator 带频率转换积分器的2.5 ghz 4.2 db NF直接ΔΣ接收器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942099
Mikko Englund, K. B. Ostman, O. Viitala, M. Kaltiokallio, K. Stadius, J. Ryynänen, K. Koli
{"title":"A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator","authors":"Mikko Englund, K. B. Ostman, O. Viitala, M. Kaltiokallio, K. Stadius, J. Ryynänen, K. Koli","doi":"10.1109/ESSCIRC.2014.6942099","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942099","url":null,"abstract":"This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130891558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extraction 用于高斯金字塔提取的26.5 nJ/px 2.64 Mpx/s CMOS视觉传感器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942084
Manuel Suárez-Cambre, V. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello, Á. Rodríguez-Vázquez
{"title":"A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extraction","authors":"Manuel Suárez-Cambre, V. Brea, J. Fernández-Berni, R. Carmona-Galán, D. Cabello, Á. Rodríguez-Vázquez","doi":"10.1109/ESSCIRC.2014.6942084","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942084","url":null,"abstract":"This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. The chip, manufactured in a 0.18 μm CMOS technology, consists of an arrangement of 88 × 60 processing elements (PEs) which captures images of 176 × 120 resolution and performs concurrent parallel processing right at pixel level. The Gaussian pyramid is generated by using a switched-capacitor network. Every PE includes four photodiodes, four MiM capacitors, one 8-bit single-slope ADC and one CDS circuit, occupying 44 × 44 μm2. Suitability of the chip is assessed by using metrics pertaining to visual tracking.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125464077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio 电感供电直接耦合64通道斩波稳定癫痫反应神经刺激器与数字偏移抵消和三波段无线电
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942030
Hossein Kassiri, Arezu Bagheri, N. Soltani, K. Abdelhalim, Hamed Mazhab-Jafari, M. T. Salam, J. L. Velazquez, R. Genov
{"title":"Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio","authors":"Hossein Kassiri, Arezu Bagheri, N. Soltani, K. Abdelhalim, Hamed Mazhab-Jafari, M. T. Salam, J. L. Velazquez, R. Genov","doi":"10.1109/ESSCIRC.2014.6942030","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942030","url":null,"abstract":"An inductively powered 0.13μm CMOS neurostimulator SoC for intractable epilepsy treatment is presented. Digital offset cancellation yields a compact 0.018mm2 DC-coupled neural recording front-end. Input chopper stabilization is performed on all 64 channels resulting in a 4.2μVrms input-referred noise. A tri-band FSK/UWB radio provides a versatile transcutaneous interface. The inductive powering system includes a 20mm × 20mm 8-layer flexible receiver coil with 40% power transfer efficiency. In-vivo chronic epilepsy treatment experimental results show an average sensitivity and specificity of seizure detection of 87% and 95%, respectively, with over 76% of all seizures aborted.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121090344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration 时间交错16位，250MS/s ADC，采用混合电压/电流模式架构，前景校准
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942021
Y. Haque, Donald E. Lewis, Rex Hales, R. J. Kier, Tracy Johancsik, P. T. Watkins, W. Picken, Marcellus Harper, Shyam Dujari
{"title":"Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration","authors":"Y. Haque, Donald E. Lewis, Rex Hales, R. J. Kier, Tracy Johancsik, P. T. Watkins, W. Picken, Marcellus Harper, Shyam Dujari","doi":"10.1109/ESSCIRC.2014.6942021","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942021","url":null,"abstract":"A 16b/250 MS/s ADC employs two time-interleaved ADCs with key mismatch errors calibrated in the analog domain. The ADC achieves 73.4dB SNR and 88dBFS SFDR with a 170MHz input signal. It consumes 750mW power. Die size is 3.5mm × 3.5mm in a 0.18μm CMOS process.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121241222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A very compact CMOS instrumentation amplifier with nearly rail-to-rail input common mode range 一个非常紧凑的CMOS仪表放大器，具有近轨到轨输入共模范围
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942087
P. Bruschi, F. D. Cesta, A. N. Longhitano, M. Piotto, R. Simmarano
{"title":"A very compact CMOS instrumentation amplifier with nearly rail-to-rail input common mode range","authors":"P. Bruschi, F. D. Cesta, A. N. Longhitano, M. Piotto, R. Simmarano","doi":"10.1109/ESSCIRC.2014.6942087","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942087","url":null,"abstract":"This paper presents a compact, fully-differential instrumentation amplifier with nearly rail-to-rail input common mode range. The amplifier, which is based on an original topology, embodies chopper modulation for offset and flicker noise reduction. The paper describes the experimental results obtained with a prototype designed with the UMC 0.18 μm MM/RF CMOS process. The amplifier draws 42 μA at a supply voltage of 1.8 V with an input noise voltage density of 75 nV/sqrt(Hz). Total amplifier area is 0.056 mm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132369006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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