Y. Haque, Donald E. Lewis, Rex Hales, R. J. Kier, Tracy Johancsik, P. T. Watkins, W. Picken, Marcellus Harper, Shyam Dujari
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Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration
A 16b/250 MS/s ADC employs two time-interleaved ADCs with key mismatch errors calibrated in the analog domain. The ADC achieves 73.4dB SNR and 88dBFS SFDR with a 170MHz input signal. It consumes 750mW power. Die size is 3.5mm × 3.5mm in a 0.18μm CMOS process.