An improved low-power CMOS thyristor-based micro-to-millisecond delay element

We present a novel low-power CMOS thyristor-based delay element for delay durations in the micro- to millisecond ranges. Starting from a basic CMOS thyristor delay circuit, we propose several modifications to reduce the energy/delay ratio by a factor of four: The threshold voltage of the internal CMOS thyristor is raised and a pull-up/down current source is used to increase the delay duration and reduce the influence of subthreshold leakage current on integration time and nonlinearity. A second CMOS thyristor stage increases the steepness of the transition slopes, thereby reducing shunt currents in subsequent stages during the switching event. The circuit was designed and fabricated in a commercial 0.35-μm CMOS process. Measurements were performed on a ring oscillator comprising three instances of the proposed delay element. By varying the bias currents of the elements, the delay duration can be tuned over more than three decades from 4 μs to 22 ms with excellent linearity.