ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)最新文献_第3页

A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization 41毫瓦30 gb /s CMOS光接收机，数字可调级联均衡

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942038

Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, W. Ki, P. Chiang, C. Yue

引用次数: 13

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS 一种采用22nm CMOS的16gb /s直流漂移补偿轨对轨交流耦合和无源线性均衡器的接收机

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942115

P. Francese, T. Toifl, M. Braendli, P. Buchmann, T. Morf, M. Kossel, C. Menolfi, L. Kull, T. Andersen, Hazar Yueksel

引用次数: 6

A 9.1–12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction 基于底钉压偏技术的28nm CMOS 9.1-12.7 GHz压控振荡器，用于数字变容管应力减小

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942027

B. Hershberg, K. Raczkowski, K. Vaesen, J. Craninckx

引用次数: 16

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC 用于67 dB SNDR 1.36 mW 170 MS/s的流水线SAR ADC的互补动态剩余放大器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942060

Badr Malki, B. Verbruggen, P. Wambacq, K. Deguchi, M. Iriguchi, J. Craninckx

引用次数: 32

Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology 采用40nm CMOS技术的单电感四输出开关转换器，具有优先调度程序，可实现快速瞬态和无限负载范围

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942048

Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, C. Hung, Chinder Wey, Hsin-Yu Luo

{"title":"Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology","authors":"Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, C. Hung, Chinder Wey, Hsin-Yu Luo","doi":"10.1109/ESSCIRC.2014.6942048","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942048","url":null,"abstract":"System-on-a-chip (SoC) applications need multiple power supplies with low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for single inductor quad output (SIQO) switching converter to manage energy delivery for four outputs. Consequently, SIQO converter with PSP can provides fast transient response and reduce cross-regulation. Besides, the level bypass detector (LBD) provides unlimited load range between each output through the shared inductor. The PSP cooperates with the LDB to transfer energy to low priority outputs to avoid overshoot at high priority outputs. With the two low-dropout regulator (LDR) working as buffers at low priority outputs, voltage disturbance can be filtered out. The SIQO converter fabricated in 40nm CMOS technology satisfies power requirements in portable electronics with 0.2% low noise, 15μs fast transient response, and cross-regulation smaller than 30mV.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A highly sensitive frontend IC for very robust capacitive vortex flowmeter sensors 一个高灵敏度的前端IC非常稳健的电容涡流流量计传感器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942081

H. Schmid, A. Huber, Dirk Sutterlin, Werner Tanner

引用次数: 1

A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR 50V输入范围14bit 250kS/s ADC, SFDR 97.8dB，信噪比80.2dB

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942024

Ilter Özkaya, Cagri Gurleyuk, Atilim Ergul, Arda Akkaya, D. Y. Aksin

引用次数: 10

A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation 一种32通道模块化双向神经接口系统，内置DSP进行闭环操作

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942031

P. Cong, P. Karande, Jonathan Landes, Rob Corey, S. Stanslaski, W. Santa, R. Jensen, Forrest Pape, D. Moran, T. Denison

{"title":"A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation","authors":"P. Cong, P. Karande, Jonathan Landes, Rob Corey, S. Stanslaski, W. Santa, R. Jensen, Forrest Pape, D. Moran, T. Denison","doi":"10.1109/ESSCIRC.2014.6942031","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942031","url":null,"abstract":"A prototype bi-directional neural interface system is presented with closed-loop and embedded DSP capabilities. The system includes 32-electrode stimulation capability, eight multiplexed low-noise low-power bio-potential sensing channels with on-chip digital FFT, and a Cortex M3-based microcontroller for implementing closed-loop algorithms. The stimulation subsystem can provide a maximum stimulation current of 12mA with approximately 3% accuracy per channel. The sensing subsystem uses a fully differential chopping amplifier achieving a noise floor <;100nV/rtHz with approximately 1μA current from 2V supply. A 13bit continuous-time sigma-delta ADC is used to sample the amplifier output at the rate of 33kHz. The ADC consumes approximately 100nA while achieving an ENOB of 12b with a 250Hz date rate. A hardware implementation of a cached-FFT is included in the sensing IC to perform spectral analysis of the bio-potential signal. The resulting multiple spectral signatures can be selectively sent to the microcontroller allowing for algorithmic control of the stimulator system. The system partition was designed to minimize overall computational power while providing user flexibility. The sensing performance of the prototype has been demonstrated with 2-D cursor control in a non-human primate brain machine interface (BMI) model using 20 features simultaneously.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128934818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter 提高3电平全集成降压变换器轻载效率的部分谐振开关

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942047

W. Godycki, Bo-Jhang Sun, A. Apsel

{"title":"Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter","authors":"W. Godycki, Bo-Jhang Sun, A. Apsel","doi":"10.1109/ESSCIRC.2014.6942047","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942047","url":null,"abstract":"Fully integrated 3-level converters can provide efficient steep step down conversion ratios for on-chip digital loads such as CMPs, due to their combination of advantages of both switched capacitor and buck converters. Previous work has demonstrated monolithic designs with good efficiency at driving high current loads. However, efficiency of these converters suffers at low voltages and currents, making it difficult to drive processor sleep states. In this paper we demonstrate a part-time resonant switching scheme for a fully integrated 3-level converter in standard 65nm CMOS. The 1.9×1.1mm2 design operates from a 1.8V input and provides up to 400mA using 2 phases with continuous conduction mode. By using real time peak current detection and flyback capacitor voltage positioning, the converter achieves up to 64% efficiency for less than 0.7V output with sub-40mA current levels. Measurements show that this is a 60-80% improvement in efficiency compared to the same converter with traditional DCM mode. This results in an extension of the efficient operation range of 3-level converters supporting DVFS and potentially significant energy savings when powering microprocessor sleep states.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"295 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A robust start-up Class-C CMOS VCO based on a common mode low frequency feedback loop 基于共模低频反馈回路的c类CMOS压控振荡器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942093

Stefano Perticaroli, F. Palma

{"title":"A robust start-up Class-C CMOS VCO based on a common mode low frequency feedback loop","authors":"Stefano Perticaroli, F. Palma","doi":"10.1109/ESSCIRC.2014.6942093","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942093","url":null,"abstract":"Many Class-C CMOS VCOs have been introduced in the last decade claiming to achieve improved phase noise performance and power efficiency with apparently no tradeoff, however only in the past two years implementation efforts have been focused on stability related issues of such oscillator architectures. In fact, oscillators exploiting time-varying bias techniques may present several stability points and for this reason dedicated start-up circuits are needed to reach the desired periodic steady state regime. In this paper we introduce a novel stabilization technique for a CMOS VCO polarized in Class-C via a common mode feedback loop with the aim to ensure a robust start-up with no significant phase-noise and power efficiency degradation. The VCO core is based on a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The proposed Class-C VCO is implemented in a RF 55nm CMOS technology and is tunable over the frequency band 6.6-8.2 GHz with average phase noise lower than -127 dBc/Hz @ 1 MHz offset and mean power consumption of 18mW, for a state-of-the-art figure-of-merit of -190 dBc/Hz @ 1 MHz offset.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116597286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5