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ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 5b 12.9 µW charge-redistribution phase domain ADC for low power FSK/PSK demodulation 用于低功率FSK/PSK解调的5b 12.9µW电荷再分配相域ADC
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942075
Yao Liu, Duan Zhao, Yongjia Li, W. Serdijn
{"title":"A 5b 12.9 µW charge-redistribution phase domain ADC for low power FSK/PSK demodulation","authors":"Yao Liu, Duan Zhao, Yongjia Li, W. Serdijn","doi":"10.1109/ESSCIRC.2014.6942075","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942075","url":null,"abstract":"This paper presents a 5 bit charge-redistribution phase domain ADC (PhADC) implemented in 0.18 μm CMOS technology for low power FSK/PSK demodulation. An IQ-assisted conversion algorithm is proposed to avoid the need for an accurate linear combination of in-phase (I) and quadrature (Q) signals with various scaling factors in a conventional zerocrossing algorithm, thus eliminating the power consumption and the phase nonidealities arising from such a linear combination. A PhADC based on a charge-redistribution DAC is demonstrated as a low power implementation of the algorithm due to the energy efficient operation in the charge domain. The prototype achieves an ENOB of 4.85 bit at 1 MS/s, while dissipating 12.9 μW from a 1.2 V supply, leading to a FoM of 1.2 pJ/step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"109 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation 基于像素内解调的533pW NEP 31×31像素太赫兹图像传感器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942082
Assim Boukhayma, J. Rostaing, A. Mollard, F. Guellec, Michele Benetti, G. Ducournau, J. Lampin, A. Dupret, C. Enz, M. Tchagaspanian, J. Nicolas
{"title":"A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation","authors":"Assim Boukhayma, J. Rostaing, A. Mollard, F. Guellec, Michele Benetti, G. Ducournau, J. Lampin, A. Dupret, C. Enz, M. Tchagaspanian, J. Nicolas","doi":"10.1109/ESSCIRC.2014.6942082","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942082","url":null,"abstract":"A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the modulated THz radiation, by means of an antenna/MOSFET, then filtering the signal band using an in-pixel 16-paths passive SC-filter combined with a CT Gm-C filter resulting in a high Q factor of 100. This THz imager features a measured NEP of 533 pW at 270 GHz and 732 pW at 600 GHz respectively, and a sensitive readout chain with an input referred noise of 0.2 μVRMS.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters 折叠迪克森变换器:迈向完全集成的宽输入范围电容DC-DC变换器的一步
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942073
Athanasios Sarafianos, M. Steyaert
{"title":"The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters","authors":"Athanasios Sarafianos, M. Steyaert","doi":"10.1109/ESSCIRC.2014.6942073","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942073","url":null,"abstract":"This paper presents a novel approach to wide input range capacitive DC-DC converters. The star connected Dickson converter is used, not only for its low bottom plate voltage swing and efficient use of switches, but also for its very regular structure. This regular structure allows it to operate as a folding Dickson converter, implementing several conversion ratios, as well as reusing all of its flying capacitance. Folding is achieved by changing the phases of the switches, and keeping certain flying switches on in both phases, virtually lumping flying capacitors together. This last fact, along with the other benefits of the Dickson converter, makes it a good candidate for full integration. The flying switches of the converter are driven from their own converter, using an adapted bootstrapped converter which uses the intrinsic operation of the Dickson converter to copy the voltage of the flying capacitors and boost it by Vout.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"72 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114314108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automotive electronics: Application & technology megatrends 汽车电子:应用与技术大趋势
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942016
F. Marchio, B. Vittorelli, Roberto Colombo
{"title":"Automotive electronics: Application & technology megatrends","authors":"F. Marchio, B. Vittorelli, Roberto Colombo","doi":"10.1109/ESSCIRC.2014.6942016","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942016","url":null,"abstract":"The complexity of the requirements for automotive applications is increasing at an astonishing pace. Concepts from other domains are being introduced in order to address these demands. For example we now need to cover fault tolerant and failsafe systems. The functional safety of systems, products and processes increases with every day and with every new development and we must maintain a grasp of the risks during every phase: from the first concept through development and from operation through shutdown. With the increased connectivity and complexity there are serious security challenges for the design of automotive hardware/software architectures due to attacks. Virtualization is now being made available in automotive embedded environments providing developers with the ultimate open platform: the ability to run any flavor of operating system in any combination, creating an unprecedented flexibility for deployment and usage. With the immense processing power that is being unlocked with multi-processor systems we are now able to address complex issues such as a complete inspection of the vehicle's environment. In this paper we will discuss the challenges of implementing a safe, secure, complex driver assistance system that paves the way towards autonomous driving.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125158970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control 一个0.171 mw, 2.4 ghz，动态电源电压控制的d类压控振荡器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942091
Y. Yoshihara, H. Majima, R. Fujimoto
{"title":"A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control","authors":"Y. Yoshihara, H. Majima, R. Fujimoto","doi":"10.1109/ESSCIRC.2014.6942091","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942091","url":null,"abstract":"A low-voltage, low-power class-D VCO is presented. An LDO based dynamic supply voltage control technique for the class-D VCO is proposed, which realizes fast and reliable start-up and extremely low-voltage operation of the class-D VCO. The proposed LDO-VCO is fabricated using a 28 nm CMOS technology. The measured phase noise is -115.9 dBc/Hz at 1 MHz offset from the 2.35 GHz carrier, while drawing the current of 760 μA from 0.5 V LDO input. The class-D VCO core consumes 0.171 mW from 225 mV LDO output and the FoM is 191.0 dBc/Hz.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124190327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS 5阶gm-C低通滤波器，截止频率精度为±3%，调谐范围为220MHz至3.3GHz，采用28nm LP CMOS
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942094
Nicolo Sabatino, Gabriele Minoia, M. Roche, D. Baldi, E. Temporiti, A. Mazzanti
{"title":"A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS","authors":"Nicolo Sabatino, Gabriele Minoia, M. Roche, D. Baldi, E. Temporiti, A. Mazzanti","doi":"10.1109/ESSCIRC.2014.6942094","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942094","url":null,"abstract":"A 5th order gm-C filter complete with calibration circuits with wide tuning range and cut-off frequency up to the GHz range is presented. To simplify calibrations, integrators are designed to have a relatively low static gain of 32dB, regulated with negative resistors. Transconductance and gain are continuously controlled with a master-slave approach leading to a remarkably stable filter shape and cut-off frequency accuracy within ±3% over a 0°-100° temperature range and ±5% supply variation. A test-chip has been realized in a 28nm Low Power CMOS technology. The cut-off frequency is tunable from 220MHz to 3.3GHz with power dissipation scaling from 5mW to 30mW. THD is -40dB at -24dBV input signal while the integrated input equivalent noise is lower than 400μVrms, corresponding to an SNR better than 39dB.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS 13fJ/bit探测弹性250K PUF阵列，软暗位掩蔽，22nm三门CMOS误码率为1.94%
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942066
Sudhir K. Satpathy, S. Mathew, Jiangtao Li, Patrick Koeberl, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy
{"title":"13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS","authors":"Sudhir K. Satpathy, S. Mathew, Jiangtao Li, Patrick Koeberl, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy","doi":"10.1109/ESSCIRC.2014.6942066","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942066","url":null,"abstract":"A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing bit-error down to 1.94%. Transient behavior of the hybrid PUF cell, along with the use of balanced local clock routing improves resiliency to invasive power-up probing attacks by 75%.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 500MHz– 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering 一个500MHz - 2.7 GHz的8路编织下变频器，具有谐波抑制和嵌入式滤波
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942062
R. Struiksma, E. Klumperink, B. Nauta, F. V. Vliet
{"title":"A 500MHz– 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering","authors":"R. Struiksma, E. Klumperink, B. Nauta, F. V. Vliet","doi":"10.1109/ESSCIRC.2014.6942062","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942062","url":null,"abstract":"This paper describes a combination of a Weaver mixer and an N-path filter for a superheterodyne receiver with a reconfigurable frequency plan. It uses an N-path topology driven with two different frequencies, effectively realizing a frequency shift together with band-pass filtering. To reduce transfers via harmonics other than the fundamental, a harmonic rejection scheme is used. A 28nm FDSOI CMOS implementation with 30 dB harmonic rejection and an out-of-band IIP3 of >20dBm is demonstrated.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114818461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration 12b 53 mW 195 MS/s流水线ADC, 82dB SFDR，采用分体式ADC校准
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942023
R. Sehgal, Frank M. L. van der Goes, K. Bult
{"title":"A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration","authors":"R. Sehgal, Frank M. L. van der Goes, K. Bult","doi":"10.1109/ESSCIRC.2014.6942023","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942023","url":null,"abstract":"A 12-bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered in order to achieve higher energy efficiency, and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical opamp implementation, the power consumption of the residue amplifier was reduced by roughly 70% in the first two stages and by 50% in the remaining stages. The ADC was implemented in 40nm digital CMOS and shows a Schreier figure-of-merit of 157.4 dB at 1V supply, sampling at 195MS/s, with an SNDR/SFDR of 64.77dB/82dB.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129265078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique 采用低共噪声嵌入式单电感双极输出功率模块和动态升压技术的d类放大器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942085
Shin-Hao Chen, Kuei-Liang Lin, S. Ng, Ke-Horng Chen, Chinder Wey, Sheng Kang, Kevin Cheng, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo
{"title":"A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique","authors":"Shin-Hao Chen, Kuei-Liang Lin, S. Ng, Ke-Horng Chen, Chinder Wey, Sheng Kang, Kevin Cheng, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo","doi":"10.1109/ESSCIRC.2014.6942085","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942085","url":null,"abstract":"This paper proposes a high efficiency Class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter's bipolar outputs not only suppress equivalent common mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability, CDA is capable of operating in both single-ended (SE) and bridge-tide load (BTL) configurations. Furthermore, the proposed dynamic voltage boosting (DVB) technique adjusts the SIBO output voltage level according to the CDA's output level with 5% power efficiency improvement. Peak total harmonic distortion plus noise (THD+N) performance is 0.012%. Peak power efficiency of SIBO and CDA are 89% and 93.2%, respectively.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129648210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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