13fJ/bit探测弹性250K PUF阵列，软暗位掩蔽，22nm三门CMOS误码率为1.94%

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI:10.1109/ESSCIRC.2014.6942066

Sudhir K. Satpathy, S. Mathew, Jiangtao Li, Patrick Koeberl, M. Anders, Himanshu Kaul, Gregory K. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy

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引用次数: 26

摘要

采用22nm三栅极CMOS，制备了一种工作频率为2GHz、总功耗为13fJ/bit、工作电压为0.9V、温度为25℃的250K探针弹性PUF阵列。混合PUF电路集成了负载调制和运行时软暗位掩模生成，能够以100%的精度识别不稳定的PUF位，无需多次电压/温度表征，同时将误码率降低到1.94%。混合PUF单元的瞬态行为，以及平衡本地时钟路由的使用，将入侵性上电探测攻击的弹性提高了75%。

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13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing bit-error down to 1.94%. Transient behavior of the hybrid PUF cell, along with the use of balanced local clock routing improves resiliency to invasive power-up probing attacks by 75%.

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ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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