ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)最新文献_第5页

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity 支持软输出均衡和Rx分集的EDGE PHY ASIC

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942057

Harald Kröll, S. Zwicky, Benjamin Weber, C. Roth, C. Benkeser, A. Burg, Qiuting Huang

引用次数: 7

A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS 用于28纳米低漏CMOS突发模式移动存储器I/O的3.2 ghz 1.3 mw ILO相位旋转器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942119

M. Aleksic

引用次数: 5

A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs 利用亚阈值ota的250mV 77dB DR 10kHz BW SC ΔΣ调制器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942111

Zhiliang Qiao, Xiong Zhou, Qiang Li

引用次数: 17

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS 基于40nm CMOS的6.2mW 7b 3.5GS/s时间交错2级流水线ADC

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942025

A. Spagnolo, B. Verbruggen, S. D’Amico, P. Wambacq

引用次数: 8

A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters 一种50V高速电平转换器，具有高dv/dt抗扰度，适用于多mhz DCDC转换器

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942044

J. Wittmann, Thoralf Rosahl, B. Wicht

{"title":"A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters","authors":"J. Wittmann, Thoralf Rosahl, B. Wicht","doi":"10.1109/ESSCIRC.2014.6942044","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942044","url":null,"abstract":"Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126930847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3 线性28纳米CMOS数字发射机，2×12bit高达LO基带采样和- 58dBc C-IM3

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942101

M. Ingels, Xiaoqiang Zhang, K. Raczkowski, S. Cha, P. Palmers, J. Craninckx

引用次数: 10

A 4th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS 4阶Gm-C滤波器，10MHz带宽，39dBm IIP3, 65nm CMOS

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942098

Mohammed Abdulaziz, Markus Törmänen, H. Sjöland

引用次数: 6

A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process 一个600µA 32 kHz输入960 MHz输出的CP-PLL，在28nm FD-SOI工艺中具有530ps集成抖动

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942028

A. Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda

引用次数: 3

A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference 一个490-nA, 43-ppm/°C，低于0.8 v电源电压基准

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942035

P. B. Basyurt, D. Y. Aksin, E. Bonizzoni, F. Maloberti

引用次数: 5

A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering 一个195.6dBc/Hz峰值FoM P-N b类振荡器，基于变压器的尾部滤波

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942089

Marco Garampazzi, P. Mendes, Nicola Codega, D. Manstretta, R. Castello

引用次数: 9