Harald Kröll, S. Zwicky, Benjamin Weber, C. Roth, C. Benkeser, A. Burg, Qiuting Huang
{"title":"An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity","authors":"Harald Kröll, S. Zwicky, Benjamin Weber, C. Roth, C. Benkeser, A. Burg, Qiuting Huang","doi":"10.1109/ESSCIRC.2014.6942057","DOIUrl":null,"url":null,"abstract":"In this paper the first complete Evolved EDGE transceiver physical layer ASIC supporting receive diversity and soft-output Viterbi equalization is presented. It comprises transmitter and receiver with detector and a decoder with an autonomous incremental redundancy implementation. The ASIC reaches a measured sensitivity of -111.8dBm for single antenna GSM voice channels and achieves the reference interference performance for adjacent channels 12 dB above 3GPP requirements. It occupies 6mm2 in 130nm CMOS with a power consumption between 5 and 39mW.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this paper the first complete Evolved EDGE transceiver physical layer ASIC supporting receive diversity and soft-output Viterbi equalization is presented. It comprises transmitter and receiver with detector and a decoder with an autonomous incremental redundancy implementation. The ASIC reaches a measured sensitivity of -111.8dBm for single antenna GSM voice channels and achieves the reference interference performance for adjacent channels 12 dB above 3GPP requirements. It occupies 6mm2 in 130nm CMOS with a power consumption between 5 and 39mW.