{"title":"用于28纳米低漏CMOS突发模式移动存储器I/O的3.2 ghz 1.3 mw ILO相位旋转器","authors":"M. Aleksic","doi":"10.1109/ESSCIRC.2014.6942119","DOIUrl":null,"url":null,"abstract":"This paper presents a 7-bit 3.2-GHz injection-locked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved by strong injection, as opposed to a relatively weak injection during normal operation, and 2) phase characteristic calibration that allows continuous, infinite-throw phase rotation needed for link timing calibration. The circuit is implemented in a 1-V low-leakage 28-nm CMOS process. Power consumption and area are 1.3 mW and 0.03 mm2.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS\",\"authors\":\"M. Aleksic\",\"doi\":\"10.1109/ESSCIRC.2014.6942119\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 7-bit 3.2-GHz injection-locked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved by strong injection, as opposed to a relatively weak injection during normal operation, and 2) phase characteristic calibration that allows continuous, infinite-throw phase rotation needed for link timing calibration. The circuit is implemented in a 1-V low-leakage 28-nm CMOS process. Power consumption and area are 1.3 mW and 0.03 mm2.\",\"PeriodicalId\":202377,\"journal\":{\"name\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2014.6942119\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS
This paper presents a 7-bit 3.2-GHz injection-locked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved by strong injection, as opposed to a relatively weak injection during normal operation, and 2) phase characteristic calibration that allows continuous, infinite-throw phase rotation needed for link timing calibration. The circuit is implemented in a 1-V low-leakage 28-nm CMOS process. Power consumption and area are 1.3 mW and 0.03 mm2.