ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)最新文献

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Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC 时钟和同步网络的3GHz 64位ARMv8 8核SoC
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942068
L. Ravezzi, H. Partovi, Dong Wang, C. Wang, Ronen Cohen, M. Ashcraft, A. Yeung, Qawi Harvard, Russell Homer, J. Ngai, G. Favor
{"title":"Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC","authors":"L. Ravezzi, H. Partovi, Dong Wang, C. Wang, Ronen Cohen, M. Ashcraft, A. Yeung, Qawi Harvard, Russell Homer, J. Ngai, G. Favor","doi":"10.1109/ESSCIRC.2014.6942068","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942068","url":null,"abstract":"This paper describes the clock distribution and synchronization network for a 64bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40nm CMOS technology and operates at 3.0GHz. The system PLL has a measured rms jitter <;1psec and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;9psec of skew (2.7% of clock period). By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitudes and thus is suited for high speed synchronization operations, is proposed.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR 1.5nJ/像素超分辨率增强型FAST拐角检测处理器,实现高精度AR
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942054
Seongwook Park, Gyeonghoon Kim, Junyoung Park, H. Yoo
{"title":"A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR","authors":"Seongwook Park, Gyeonghoon Kim, Junyoung Park, H. Yoo","doi":"10.1109/ESSCIRC.2014.6942054","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942054","url":null,"abstract":"Most vision applications such as object recognition and augmented reality require a high resolution image because their performance is heavily dependent on a local feature point like an edge and a corner. Unfortunately, the vulnerability of correct feature detection always exists in vision applications. Moreover, it is hard to increase image resolution because there is the trade-off between the image resolution and the system power consumption in a wearable device. To resolve this, we present an energy-efficient Features from Accelerated Segment Test (FAST) corner detection processor with a high-throughput super-resolution 4-core cluster for low-power and high accuracy AR applications. To perform high throughput super-resolution, the hardware is proposed with an adaptive multi-issue multiply-accumulate (AMMAC) unit and a shift register (SHR) based angle integrator. Finally, a proposed super-resolution enhanced FAST corner detection processor performs 13.51% detection accuracy enhanced FAST corner detection on up to a 16× super-resolution image with only 1.5nJ/pixel energy efficiency.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125421323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications 一个0.2nJ/像素4K 60fps的Main-10 HEVC解码器,具有多格式功能,适用于超高清电视应用
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942055
Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai
{"title":"A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai","doi":"10.1109/ESSCIRC.2014.6942055","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942055","url":null,"abstract":"A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multi-standard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm2. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications 5mW多标准蓝牙LE/IEEE 802.15.6 SoC,用于WBAN应用
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942077
Gabriele Devita, A. Wong, M. Dawkins, K. Glaros, U. Kiani, Franco Lauria, V. Madaka, O. Omeni, J. Schiff, A. Vasudevan, L. Whitaker, S. Yu, A. Burdett
{"title":"A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications","authors":"Gabriele Devita, A. Wong, M. Dawkins, K. Glaros, U. Kiani, Franco Lauria, V. Madaka, O. Omeni, J. Schiff, A. Vasudevan, L. Whitaker, S. Yu, A. Burdett","doi":"10.1109/ESSCIRC.2014.6942077","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942077","url":null,"abstract":"In this work we present Bodysense, a low-power radio with sensor interface for WBAN applications. The SoC comprises a transceiver operating in the frequency range 2.36-2.483GHz and adhering to the IEEE 802.15.6 Narrow Band (NB) and Bluetooth Low-Energy (BLE) standards. The chip was fabricated in a 65nm technology and absorbs 5.5mA/5mA when operating in Rx/Tx mode. The receiver noise figure of 6dB leads to excellent sensitivity in both standards (-94/-96 for the BLE/NB). The π/4-DQPSK transmitter has a measured EVM and ACPR of 6.8% and -30dBc that exceed the NB specifications.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132078510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing 一个完全集成的d类放大器在40nm CMOS具有动态级联码偏置和负载电流传感
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942086
V. Binet, F. Amiard, E. Allier, S. Valcin, A. Nagari
{"title":"A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing","authors":"V. Binet, F. Amiard, E. Allier, S. Valcin, A. Nagari","doi":"10.1109/ESSCIRC.2014.6942086","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942086","url":null,"abstract":"To address in the same time high efficiency, high output power and high complexity functions for Signal Processing systems, the partitioning tends to integrate in the same chip some functions of the digital (like DSP) and audio amplifiers (like Class-D) in a deep submicron technology. To fulfill high output power demand without compromising the device's reliability constraints, the amplifier power-stage use cascoded structure. In this paper a new design aimed to decrease the power stage consumption adapting the cascode bias of power stage branches during its switching is presented without impacting the MOS device's reliability. In addition, a fully integrated load current sensing, independent from any process, package or temperature spread, suitable for Class-D speaker protection systems, is explained. The circuit has been implemented in 40nm CMOS technology.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters 一个0.21 v的最小输入,73.6%的最高效率,完全集成电压升压转换器与MPPT低压能量采集器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942070
Toshihiro Ozaki, T. Hirose, T. Nagai, Keishi Tsubaki, N. Kuroki, M. Numa
{"title":"A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters","authors":"Toshihiro Ozaki, T. Hirose, T. Nagai, Keishi Tsubaki, N. Kuroki, M. Numa","doi":"10.1109/ESSCIRC.2014.6942070","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942070","url":null,"abstract":"This paper proposes a fully integrated voltage boost converter with a maximum power point tracking (MPPT) circuit for ultra-low power energy harvesting. The converter is based on a conventional charge pump circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient switching operation. The MPPT circuit we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input of 0.21 V.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129371654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer 40MHz-BW 35fJ/步进非线性对消两步ADC,双输入vco量化器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942022
Peng Zhu, Xinpeng Xing, G. Gielen
{"title":"A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer","authors":"Peng Zhu, Xinpeng Xing, G. Gielen","doi":"10.1109/ESSCIRC.2014.6942022","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942022","url":null,"abstract":"This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130752261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies 采用PIC25G和65nm CMOS技术的3d集成25Gbps硅光子接收器
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942039
E. Temporiti, Gabriele Minoia, M. Repossi, D. Baldi, A. Ghilioni, F. Svelto
{"title":"A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies","authors":"E. Temporiti, Gabriele Minoia, M. Repossi, D. Baldi, A. Ghilioni, F. Svelto","doi":"10.1109/ESSCIRC.2014.6942039","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942039","url":null,"abstract":"Silicon photonics platforms are emerging as attractive solutions for low power and cost effective short/medium-reach optical interconnects. To overcome the intrinsic limitations of monolithically integrated photonics with electronics, STMicroelectronics has developed a 3D-compatible silicon photonics platform that implements in the FEOL only optical devices. Photonics Integrated Circuits are made compatible with 3D assembly of Electronic Integrated Circuits through the use of copper pillars. In this paper we present a 25Gbps Opto-Electronic receiver operating at 1310nm wavelength, consisting of an integrated waveguide Germanium photodiode interfaced by means of copper pillars to a 65nm CMOS amplification chain. The receiver demonstrates an Average Optical Power sensitivity at photodiode input, at a BER of 10-12, of -11.9dBm with a PRBS7 input signal, corresponding to a 97μApp TIA input current. The achieved sensitivity is ~6dB better than state-of-the-art monolithically integrated silicon photonics receivers, at comparable TIA and LA power consumption.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115915972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance 一种具有高压输入多路复用器的神经记录IC,用于电压和电流刺激,符合18V
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942032
U. Bihr, J. Anders, J. Rickert, M. Schuettler, A. Moeller, K. Boven, J. Becker, M. Ortmanns
{"title":"A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance","authors":"U. Bihr, J. Anders, J. Rickert, M. Schuettler, A. Moeller, K. Boven, J. Becker, M. Ortmanns","doi":"10.1109/ESSCIRC.2014.6942032","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942032","url":null,"abstract":"This paper presents an innovative ASIC design used in a high voltage (HV) neuromodulation system-in-package (SiP). A HV input switching network offers synchronous neural recording at 32 electrodes and independent stimulation on two selectable electrodes with up to 15mA and 18V input compliance. In addition, it provides artifact canceling and enables the use of different supply voltages for stimulator and recorder. Thus, a HV stimulator can be combined with a high efficient LV neural recorder design. Frequency separation of the local field potentials (LFP) and action potentials (AP) with individually adjustable gain and frequency settings via switched capacitor filter structures implicitly improves the input referred quantization error. The LFP low corner frequency can be measured reproducibly at 60mHz and the measured input referred noise is 3.3 μVrms for both, the AP and LFP band. The design is implemented in a 180nm HV CMOS technology, has a die size of 3.8mm × 4.3mm and a power consumption of 4.5mW.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Ultra Low Power short range radios: Covering the last mile of the IoT 超低功率短距离无线电:覆盖物联网的最后一英里
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI: 10.1109/ESSCIRC.2014.6942020
K. Philips
{"title":"Ultra Low Power short range radios: Covering the last mile of the IoT","authors":"K. Philips","doi":"10.1109/ESSCIRC.2014.6942020","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942020","url":null,"abstract":"Short Range Radios are predicted to realize a paradigm change by 2020, similar to the revolution of mobile communication, in the nineties. These radios provide the last mile wireless connectivity between “things” and the Internet. They connect your new wearable devices to your smart phone, or enable smart energy monitoring and control in your home. In this paper, we analyze the power breakdown of such new consumer devices operating from small, advanced batteries. It is shown that the wireless connectivity has a dominant impact on the overall power budget of these devices. Today, short range radios with Ultra-Low Power (ULP) consumption, in the range of a few mW, are reported. It is shown that future small and flexible sensor nodes need wireless connectivity at sub-mW “U2LP” consumption. An overview of state-of-the-art short range transceivers reveals promising architectures and circuits to reach the U2LP target.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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