A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2014-11-03 DOI:10.1109/ESSCIRC.2014.6942055

Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, P. Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai

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引用次数: 17

Abstract

A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted memory management unit (W-MMU) and multi-standard architecture reduce DRAM bandwidth and cost by 43% and 28%, respectively. This 4K Main-10 HEVC video decoder chip integrates 3.4M gate counts with area of 2.86mm2. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [6] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback for UHD-TV applications.

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一个0.2nJ/像素4K 60fps的Main-10 HEVC解码器，具有多格式功能，适用于超高清电视应用

在28纳米CMOS工艺中，首次报道了集成14种视频格式的4kx 2K@60fps和Main-10 HEVC视频解码器。它采用自适应编码单元平衡(ACUB)和数据共享波前双核(DSWD)架构，将所需的工作频率降低了65%。提出了一种10位智能像素存储(SPS)方案，可将帧缓冲空间减少37.5%。此外，加权内存管理单元(W-MMU)和多标准架构将DRAM带宽和成本分别降低了43%和28%。这款4K Main-10 HEVC视频解码器芯片集成了3.4万个门数，面积为2.86mm2。它实现了5.3亿像素/秒的吞吐量，是最先进的HEVC设计[6]的两倍，能耗为0.2nJ/像素，可实现超高清电视应用的实时4K视频播放。

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ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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