A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing

Abstract

To address in the same time high efficiency, high output power and high complexity functions for Signal Processing systems, the partitioning tends to integrate in the same chip some functions of the digital (like DSP) and audio amplifiers (like Class-D) in a deep submicron technology. To fulfill high output power demand without compromising the device's reliability constraints, the amplifier power-stage use cascoded structure. In this paper a new design aimed to decrease the power stage consumption adapting the cascode bias of power stage branches during its switching is presented without impacting the MOS device's reliability. In addition, a fully integrated load current sensing, independent from any process, package or temperature spread, suitable for Class-D speaker protection systems, is explained. The circuit has been implemented in 40nm CMOS technology.