Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC

This paper describes the clock distribution and synchronization network for a 64bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40nm CMOS technology and operates at 3.0GHz. The system PLL has a measured rms jitter <;1psec and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;9psec of skew (2.7% of clock period). By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitudes and thus is suited for high speed synchronization operations, is proposed.