提高3电平全集成降压变换器轻载效率的部分谐振开关

W. Godycki, Bo-Jhang Sun, A. Apsel
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引用次数: 11

摘要

由于完全集成的3电平转换器结合了开关电容和降压转换器的优点,可以为片上数字负载(如cmp)提供高效的陡峭降压转换比率。先前的工作已经证明单片设计在驱动大电流负载方面具有良好的效率。然而,这些转换器的效率在低电压和电流下受到影响,使其难以驱动处理器休眠状态。在本文中,我们展示了一种用于标准65nm CMOS的全集成3电平变换器的部分谐振开关方案。1.9×1.1mm2设计工作从1.8V输入,并提供高达400mA使用2相连续传导模式。通过实时峰值电流检测和反激电容电压定位,变换器在低于0.7V的输出和低于40ma的电流水平下实现高达64%的效率。测量表明,与采用传统DCM模式的相同转换器相比,效率提高了60-80%。这将扩展支持DVFS的3电平转换器的有效运行范围,并在为微处理器休眠状态供电时潜在地节省大量能源。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter
Fully integrated 3-level converters can provide efficient steep step down conversion ratios for on-chip digital loads such as CMPs, due to their combination of advantages of both switched capacitor and buck converters. Previous work has demonstrated monolithic designs with good efficiency at driving high current loads. However, efficiency of these converters suffers at low voltages and currents, making it difficult to drive processor sleep states. In this paper we demonstrate a part-time resonant switching scheme for a fully integrated 3-level converter in standard 65nm CMOS. The 1.9×1.1mm2 design operates from a 1.8V input and provides up to 400mA using 2 phases with continuous conduction mode. By using real time peak current detection and flyback capacitor voltage positioning, the converter achieves up to 64% efficiency for less than 0.7V output with sub-40mA current levels. Measurements show that this is a 60-80% improvement in efficiency compared to the same converter with traditional DCM mode. This results in an extension of the efficient operation range of 3-level converters supporting DVFS and potentially significant energy savings when powering microprocessor sleep states.
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