{"title":"提高3电平全集成降压变换器轻载效率的部分谐振开关","authors":"W. Godycki, Bo-Jhang Sun, A. Apsel","doi":"10.1109/ESSCIRC.2014.6942047","DOIUrl":null,"url":null,"abstract":"Fully integrated 3-level converters can provide efficient steep step down conversion ratios for on-chip digital loads such as CMPs, due to their combination of advantages of both switched capacitor and buck converters. Previous work has demonstrated monolithic designs with good efficiency at driving high current loads. However, efficiency of these converters suffers at low voltages and currents, making it difficult to drive processor sleep states. In this paper we demonstrate a part-time resonant switching scheme for a fully integrated 3-level converter in standard 65nm CMOS. The 1.9×1.1mm2 design operates from a 1.8V input and provides up to 400mA using 2 phases with continuous conduction mode. By using real time peak current detection and flyback capacitor voltage positioning, the converter achieves up to 64% efficiency for less than 0.7V output with sub-40mA current levels. Measurements show that this is a 60-80% improvement in efficiency compared to the same converter with traditional DCM mode. This results in an extension of the efficient operation range of 3-level converters supporting DVFS and potentially significant energy savings when powering microprocessor sleep states.","PeriodicalId":202377,"journal":{"name":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","volume":"295 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter\",\"authors\":\"W. Godycki, Bo-Jhang Sun, A. Apsel\",\"doi\":\"10.1109/ESSCIRC.2014.6942047\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully integrated 3-level converters can provide efficient steep step down conversion ratios for on-chip digital loads such as CMPs, due to their combination of advantages of both switched capacitor and buck converters. Previous work has demonstrated monolithic designs with good efficiency at driving high current loads. However, efficiency of these converters suffers at low voltages and currents, making it difficult to drive processor sleep states. In this paper we demonstrate a part-time resonant switching scheme for a fully integrated 3-level converter in standard 65nm CMOS. The 1.9×1.1mm2 design operates from a 1.8V input and provides up to 400mA using 2 phases with continuous conduction mode. By using real time peak current detection and flyback capacitor voltage positioning, the converter achieves up to 64% efficiency for less than 0.7V output with sub-40mA current levels. Measurements show that this is a 60-80% improvement in efficiency compared to the same converter with traditional DCM mode. This results in an extension of the efficient operation range of 3-level converters supporting DVFS and potentially significant energy savings when powering microprocessor sleep states.\",\"PeriodicalId\":202377,\"journal\":{\"name\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"295 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2014.6942047\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2014.6942047","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter
Fully integrated 3-level converters can provide efficient steep step down conversion ratios for on-chip digital loads such as CMPs, due to their combination of advantages of both switched capacitor and buck converters. Previous work has demonstrated monolithic designs with good efficiency at driving high current loads. However, efficiency of these converters suffers at low voltages and currents, making it difficult to drive processor sleep states. In this paper we demonstrate a part-time resonant switching scheme for a fully integrated 3-level converter in standard 65nm CMOS. The 1.9×1.1mm2 design operates from a 1.8V input and provides up to 400mA using 2 phases with continuous conduction mode. By using real time peak current detection and flyback capacitor voltage positioning, the converter achieves up to 64% efficiency for less than 0.7V output with sub-40mA current levels. Measurements show that this is a 60-80% improvement in efficiency compared to the same converter with traditional DCM mode. This results in an extension of the efficient operation range of 3-level converters supporting DVFS and potentially significant energy savings when powering microprocessor sleep states.