A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter

Abstract

It is shown that memoryless analog-to-digital conversion using ΔΣ modulators is possible without resetting the modulator or decimation filters by using a suitable signal transfer function for the modulator and a decimation filter which satisfies Nyquist intersymbol interference (ISI) criterion. This architecture enables memoryless operation over the entire signal bandwidth of the ΔΣ modulator which is significantly higher than the bandwidth in incremental ΔΣ architectures in which the modulator is reset. A two-channel ADC with a total effective sampling rate of fs/64 per channel is built using a third order 32× oversampled switched-capacitor ΔΣ modulator. The prototype in 0.18 μm CMOS occupies 2.1 mm2 and consumes 59.63mW. At 16MHz (64MHz) sampling rate for the DSM, the dynamic range (DR) of the standalone modulator is 86.5 dB(85.1 dB), and that in two-channel mode, with perchannel rate of 250 kHz (1MHz) is 81 dB (80.5 dB). The maximum SNR in multiplexed mode at 16MHz (64MHz) sampling rate is 80.3 dB(68.6 dB). At both sampling rates, the inter-channel crosstalk due to maximum input on the other channel is below 77.7 dB.