Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip

Abstract

A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and AVS to further improve system efficiency. The all-digital CDR achieves state-of-the-art FOMs at 0.208 mW/Gb/s and 468.75 μm2/Gb/s. An intra-bit boosting technique helps the USB2.0 TX meet the eye mask with a 200 ps margin and reduced rise and fall times.