L. Panarella, Q. Smets, D. Verreck, T. Schram, D. Cott, I. Asselberghs, B. Kaczer
{"title":"Analysis of BTI in 300 mm integrated dual-gate WS2 FETs","authors":"L. Panarella, Q. Smets, D. Verreck, T. Schram, D. Cott, I. Asselberghs, B. Kaczer","doi":"10.1109/DRC55272.2022.9855819","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855819","url":null,"abstract":"Despite their promising performance, the majority of 2D field-effect transistor (2D FET) prototypes suffers from high bias temperature instability (BTI) [1], [2] and hysteresis [3] of their gate transfer characteristics, which lead to poor reliability [4]. For this reason, a special effort is required in order to improve the quality of gate oxides and their in-terface with 2D materials.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126520866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Surila Guglani, A. Dasgupta, M. Kao, Chenming Hu, Sourajeet Roy
{"title":"Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs","authors":"Surila Guglani, A. Dasgupta, M. Kao, Chenming Hu, Sourajeet Roy","doi":"10.1109/DRC55272.2022.9855816","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855816","url":null,"abstract":"For contemporary technology nodes, Fin Field Effect Transistors (FinFETs) as shown in Fig. 1 are considered to be the device of choice as they offer superior electrostatic control of the channel [1]. For design space explorations, device optimizations, and efficient circuit designs of FinFETs, we rely on various mathematical models ranging from Technology Computer-Aided Design tools (TCAD) which are based on accurate device physics but are computationally expensive to solve, to compact models [2], which prioritize localized accuracy and computational efficiency over high generalizability and predictive ability. For the high accuracy and predictability required for proper design optimizations, TCAD is used as the tool of choice. However, the high computational cost associated with the large number of TCAD simulations required for parametric sweeps is a major bottleneck. Here, we present a novel methodology using artificial neural network (ANN) based surrogate models that meets both the criteria of numerical efficiency and predictive accuracy simultaneously.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation","authors":"Rishab Mehra, S. T. Nibhanupudi, J. Kulkarni","doi":"10.1109/DRC55272.2022.9855783","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855783","url":null,"abstract":"Multilevel cell (MLC) Resistive Random Access Memory (RRAM) is an attractive technology option to realize ultra-high density, low-power memory arrays [1]. Traditional 1-transistor 1-resistor (1T1R) bitc ell suffers from adjacent state overlap due to the inherent RRAM variations which hinders the realization of MLC capability [2]. In this work, we evaluate an alternate 2-transistor 1-resistor (2T1R) gain-cell RRAM bitcell topology that has higher read-out dynamic range and exhibits higher process variation tolerance compared to the baseline 1T1R bitcell [3]. We perform a thorough statistical estimation and variability analysis for both single-level cell (SLC) and MLC operation. For SLC operation, 2T1R can tolerate up to 400,70 higher RRAM variations than 1T1R and up to 200% higher variations for an iso-read power comparison. For MLC operation, it is 20-30% more variation tolerant and can provide the same robustness at lower read power. The write power of both bitcells is almost identical due to similar write mechanisms.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131077790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fully Epitaxial Ferroelectric III-Nitride Semiconductors: From Materials to Devices","authors":"Ping Wang, Ding Wang, Shubham Mondal, Z. Mi","doi":"10.1109/drc55272.2022.9855651","DOIUrl":"https://doi.org/10.1109/drc55272.2022.9855651","url":null,"abstract":"Recent studies have shown that the incorporation of scandium (Sc) can transform conventional III -nitride semiconductors to be ferroelectric, with switchable polarization and significantly enhanced electrical, piezoelectric, and nonlinear optical properties. These unique characteristics, together with its tunable ultrawide bandgap, have made ScAlN one of the most promising semiconductors for future high-power, high-frequency, and high-temperature electronics, acoustic resonators and filters, micro/nano-electromechanical systems (MEMS), neuromorphic and edge computing/intelligence. Sputter deposition has been widely employed for the synthesis of ScAlN films, which show limited material quality. Recently, great progress has been made in the epitaxial growth of single-crystalline wurtzite phase ScAlN utilizing standard epitaxial approaches, including molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD), which enable the seamless integration with the mature Si-based and GaN-based technologies. To date, however, the realization of ferroelectric ScAlN has been largely limited to sputter deposition. 1 It has remained a daunting challenge to achieve single crystalline ferroelectric Sc-III-nitrides. Moreover, the currently reported ScAlN exhibits extremely high unintentional impurities (e.g., 0 and C), which severely limit their practical device application.2 Therefore, the ability to improve the material quality, realize robust ferroelectric polarization switching, and demonstrate device concepts of fully epitaxial ScAlN -based heterostructures is essential for the emerging applications of Sc-III-nitrides.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134333255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marc Jaikissoon, Jerry A. Yang, Kathryn M. Neilson, E. Pop, K. Saraswat
{"title":"Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers","authors":"Marc Jaikissoon, Jerry A. Yang, Kathryn M. Neilson, E. Pop, K. Saraswat","doi":"10.1109/DRC55272.2022.9855790","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855790","url":null,"abstract":"Strain engineering has played an important role in modern transistor technology, improving mobility in Si devices since the 90 nm node. Tensile silicon nitride (SiNx) capping layers for Si NMOS have been an effective way to enhance mobility by modifying the Si band structure [1]. 2D semiconductors such as mono-layer (IL) MoS2 are also predicted to have improved mobility under tensile strain, by reduction of intervalley scattering and effective mass [2]. However, CMOS-compatible strain techniques have yet to be demonstrated for such 2D semiconductors. Here, we demonstrate improvement in the mobility and on-state current of 1L MoS2 transistors using a high-tensile-stress SiNx capping layer. We achieve up to 47% improvement in back-gated FET (BG-FET) mobility and on-state current, then extend the technique to achieve 33% improved current drive in top-gated FETs (TG-FET), with record saturation current up to 488 µA/µm in a 200 nm long channel.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125204173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM","authors":"Saikat Chakraborty, J. Kulkarni","doi":"10.1109/DRC55272.2022.9855778","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855778","url":null,"abstract":"The unprecedented growth in the adoption of Deep Neural Networks (DNN) for variety of ML/AI applications has resulted into a data deluge [1]. Among the prevalent and emerging memories, Ferroelectric Field Effect Transistor (FeFET) based memory [2]–[4], which leverages recently discovered ferroelectric properties in Hafnium/Zirconium oxides (HZO), is very promising as along with CMOS compatibility it can offer the non-volatility, dense 1-Transitor bitcells, high speed read operation, and multi-level-cell functionality. Despite the promising attributes, critical fundamental roadblocks exist in the FeFET advancement such as high program/erase voltage (±4V), poor reliability due to thin inter-layer dielectric (ILD) experiencing high electric field and large depolarizing field degrading the retention time [1], [2]. Several works have addressed these issues by introducing a circular channel geometry in recessed-channel FeFET (C-FeFET) [5], decoupling the ferroelectric layer from the MOSFET in Ferroelectric-Metal-FET (FeMFET) [6] or by connecting multiple Metal-Ferroelectric-Metal (MFeM) capacitors to the MOSFET gate terminal forming a multiple-FeMFET [7] (Fig. 1). However, C-FeFET reduces the write voltage in a limited manner because of significant voltage drop across the ILD. FeMFET or multiple-FeMFET introduces floating intermediate node between MFeM capacitor and MOSFET gate stacks which increases the depolarizing field.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mir Muntasir Hossain, P. Pandey, Akif Aabrar, K. González-Serrano, T. Moise, John Rodriguez, K. Udayakumar, S. Datta, A. Seabaugh
{"title":"Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory: Implications for Partial State Storage","authors":"Mir Muntasir Hossain, P. Pandey, Akif Aabrar, K. González-Serrano, T. Moise, John Rodriguez, K. Udayakumar, S. Datta, A. Seabaugh","doi":"10.1109/DRC55272.2022.9855808","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855808","url":null,"abstract":"Analog weight storage in polycrystalline hafnium zirconate, HfZrO4, (HZO) ferroelectric capacitors has been widely explored for use in two-terminal ferroelectric (Fe) memory [e.g. 1–3]. Read-out in commercial Fe random access memory (FRAM) is destructive; the polarization switching current is sensed to read the charge state, followed by a data restore [4]. It is desirable to realize a nondestructive resistive read, and in this paper we utilize pulsed measurements to obtain the transient current-voltage (I-V) characteristic at switching speeds commensurate with the memory. While HZO has been shown to switch at sub-ns speeds this short switching speed is achieved using pulse voltages more than 4 times the coercive voltage (8.7 V, 10ns, 10 nm HZO), i.e. with enough field strength and duration to fully polarize the Fe [5]. In contrast, at the lower voltages used to set the polarization to an intermediate value, the settling time becomes a function of the pulse amplitude and sequence. It has been shown that current transients associated with setting the partially polarized state in HZO can be surprisingly long, even up to 1 s, depending on the pulse sequence [6]. In this paper we present a new pulse measurement protocol applied to the characterization of the transient I-V at speeds specific to the application. This data reveals the current transient associated with polarization continuation after the slew interval and can be used to validate SPICE models at pulse speeds of interest to the design.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130379305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Asmita S. Thool, Sourodeep Roy, A. Misra, B. Chakrabarti
{"title":"Controllable Defect Engineering in 2D-MoS2 for high-performance, threshold switching memristive devices","authors":"Asmita S. Thool, Sourodeep Roy, A. Misra, B. Chakrabarti","doi":"10.1109/DRC55272.2022.9855777","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855777","url":null,"abstract":"Two-dimensional (2D) materials and their hetero structures are promising for memristive applications due to their extreme scalability and high performance.1 Threshold switching in 2D-Transition Metal Dichalcogenide (TMDC) memristors has been previously identified for neuromorphic applications.2 On the other hand, accurate control of defect concentration in 2D-TMDC films is necessary for optimized performance of the memristive devices. In this work, we explore a chemical route to control defect concentration in 2D-MoS2 films. We demonstrate that the defect concentration in 2D-MoS2 can be tuned by H2O2 treatment. We then optimize the resistance switching behavior of Au/MoS2/Ag/Au memristors to obtain reliable threshold resistance switching with high on/ off ratio, low operating voltages and self-compliance behavior. This work offers promise for a low-cost, scalable approach to develop 2D-TMDC based high-performance neuromorphic hardware.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. T. Nibhanupudi, D. Veksler, A. Roy, Matthew J Coupin, Kevin C. Matthews, Jamie H. Warner, G. Bersuker, J. Kulkarni, S. Banerjee
{"title":"Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices","authors":"S. T. Nibhanupudi, D. Veksler, A. Roy, Matthew J Coupin, Kevin C. Matthews, Jamie H. Warner, G. Bersuker, J. Kulkarni, S. Banerjee","doi":"10.1109/DRC55272.2022.9855793","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855793","url":null,"abstract":"Resistive switching in 2D materials such as hexagonal boron nitride (hBN) and Transition Metal Dichalcogenides (TMDs) have been demonstrated recently [1]–[3]. These memory devices with an ultra-thin switching layer have the potential to achieve low operating voltages, low variability and are also suitable for flexible electronic applications [4]. Here we report the first experimental observation of sub-nanosecond switching of 2D hBN based resistive random access memory (RRAM) devices. This is the fastest switching speed in 2D RRAMs, surpassing the previously reported 5ns switching [5]. Devices also exhibit consistent repeatable switching between high-low memory states with ultra-short pulses (pulse-width ~ 2.7ns).","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131288090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Path Towards Realistic ASIC Electronics Deployment Into Previously Impractical Extreme Application Environments","authors":"P. Neudeck, D. Spry, M. Krasowski, Liangyu Chen","doi":"10.1109/DRC55272.2022.9855806","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855806","url":null,"abstract":"Substantial expansion of the practical environmental envelope for integrated circuit (IC) operation offers important benefits to a variety of automotive, aerospace, deep-well drilling, and manufacturing applications [1]. ICs that can reliably operate for long time periods (years) in a harsh environment without degradation or need of diagnostic/maintenance intervention enable the largest benefits compared to IC technologies requiring added shielding, cooling, remote-location, maintenance, or other overhead to perform beneficial system functions. The ability to “cold-start” at low temperature (T ≤ −55°C) and continuously function through “warm-up” to extreme temperature is also important to most applications. Fig. 1 illustrates the massive difference between a Venus lander mission that relies on sheltering electronics from the caustic 91-atmosphere pressure 460°C surface environment (600 kg lander that returns data for less than a day) compared to the mission possible with electronics that can function for long duration without need of environmental sheltering (20 kg lander that operates for 60 days) [2], [3].","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"33 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}