L. Panarella, Q. Smets, D. Verreck, T. Schram, D. Cott, I. Asselberghs, B. Kaczer
{"title":"300mm集成双栅极WS2场效应管的BTI分析","authors":"L. Panarella, Q. Smets, D. Verreck, T. Schram, D. Cott, I. Asselberghs, B. Kaczer","doi":"10.1109/DRC55272.2022.9855819","DOIUrl":null,"url":null,"abstract":"Despite their promising performance, the majority of 2D field-effect transistor (2D FET) prototypes suffers from high bias temperature instability (BTI) [1], [2] and hysteresis [3] of their gate transfer characteristics, which lead to poor reliability [4]. For this reason, a special effort is required in order to improve the quality of gate oxides and their in-terface with 2D materials.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analysis of BTI in 300 mm integrated dual-gate WS2 FETs\",\"authors\":\"L. Panarella, Q. Smets, D. Verreck, T. Schram, D. Cott, I. Asselberghs, B. Kaczer\",\"doi\":\"10.1109/DRC55272.2022.9855819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Despite their promising performance, the majority of 2D field-effect transistor (2D FET) prototypes suffers from high bias temperature instability (BTI) [1], [2] and hysteresis [3] of their gate transfer characteristics, which lead to poor reliability [4]. For this reason, a special effort is required in order to improve the quality of gate oxides and their in-terface with 2D materials.\",\"PeriodicalId\":200504,\"journal\":{\"name\":\"2022 Device Research Conference (DRC)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 Device Research Conference (DRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC55272.2022.9855819\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Device Research Conference (DRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC55272.2022.9855819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of BTI in 300 mm integrated dual-gate WS2 FETs
Despite their promising performance, the majority of 2D field-effect transistor (2D FET) prototypes suffers from high bias temperature instability (BTI) [1], [2] and hysteresis [3] of their gate transfer characteristics, which lead to poor reliability [4]. For this reason, a special effort is required in order to improve the quality of gate oxides and their in-terface with 2D materials.