Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM

Abstract

The unprecedented growth in the adoption of Deep Neural Networks (DNN) for variety of ML/AI applications has resulted into a data deluge [1]. Among the prevalent and emerging memories, Ferroelectric Field Effect Transistor (FeFET) based memory [2]–[4], which leverages recently discovered ferroelectric properties in Hafnium/Zirconium oxides (HZO), is very promising as along with CMOS compatibility it can offer the non-volatility, dense 1-Transitor bitcells, high speed read operation, and multi-level-cell functionality. Despite the promising attributes, critical fundamental roadblocks exist in the FeFET advancement such as high program/erase voltage (±4V), poor reliability due to thin inter-layer dielectric (ILD) experiencing high electric field and large depolarizing field degrading the retention time [1], [2]. Several works have addressed these issues by introducing a circular channel geometry in recessed-channel FeFET (C-FeFET) [5], decoupling the ferroelectric layer from the MOSFET in Ferroelectric-Metal-FET (FeMFET) [6] or by connecting multiple Metal-Ferroelectric-Metal (MFeM) capacitors to the MOSFET gate terminal forming a multiple-FeMFET [7] (Fig. 1). However, C-FeFET reduces the write voltage in a limited manner because of significant voltage drop across the ILD. FeMFET or multiple-FeMFET introduces floating intermediate node between MFeM capacitor and MOSFET gate stacks which increases the depolarizing field.