R. Dangi, A. Pampori, P. Kushwaha, Ekta Yadav, Santanu Sinha, Y. Chauhan
{"title":"A width-scalable SPICE compact model for GaN HEMTs including self-heating effect","authors":"R. Dangi, A. Pampori, P. Kushwaha, Ekta Yadav, Santanu Sinha, Y. Chauhan","doi":"10.1109/DRC55272.2022.9855814","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855814","url":null,"abstract":"High power operation of AlGaN/GaN HEMTs leads to a high channel temperature and heat dissipation issues which severely degrade the device reliability and power performance. Self-heating effects cannot be ignored when estimating the power performance of HEMTs, and have been an active area of research for a long time [1], [2]. Several methods used for thermal resistance measurements have been proposed in the literature, including techniques to generate comprehensive temperature profiles like infrared thermography, high-resolution Raman thermography [3], [4], etc. These thermography approaches are not always practical as they frequently require specific device samples and prohibitively expensive laboratory equipment. Pulsed measurements enable the determination of thermal resistance across a wide range of ambient temperatures [5], [6] and have been used in this work. The industry standard compact models [7]–[9] account for the self-heating effect using a thermal circuit approach involving parallel RC circuits to represent thermal time constants as shown in Fig 2(c). However, these self-heating models are valid for a narrow range of geometries and are not scalable in the truest sense (as shown in Fig. 1(a)). In this paper we presents a complete SPICE model capable of emulating the geometry-dependent self-heating behavior using a single model card.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"13 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132573615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Hoang, A. Daus, S. Wahid, Jimin Kwon, Jung-Soo Ko, S. Qin, Mahnaz Islam, K. Saraswat, H. Wong, E. Pop
{"title":"Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties","authors":"L. Hoang, A. Daus, S. Wahid, Jimin Kwon, Jung-Soo Ko, S. Qin, Mahnaz Islam, K. Saraswat, H. Wong, E. Pop","doi":"10.1109/DRC55272.2022.9855789","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855789","url":null,"abstract":"Amorphous oxide semiconductors (AOS) can be processed at low-temperature and their field-effect transistors (FETs) have demonstrated very low off-state current [1], offering promise for low-power back-end-of-line (BEOL) applications. Indium tin oxide (ITO) FETs have recently shown good characteristics [2] and good mobility (>50 cm2V−1s−1 [3]), but their stability and degradation remain unknown, e.g. given the mobility-stability trade-off in AOS [4], [5]. Here we investigate, for the first time, the influence of gate dielectric material and thickness on ITO-FET stability, which impacts bias stress through trap states. We find that HfO2 is more stable than Al2O3 as a gate dielectric for ITO FETs, which contradicts previous stability studies of other AOS.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation","authors":"Bill Zivasatienraj, W. Doolittle","doi":"10.1109/DRC55272.2022.9855650","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855650","url":null,"abstract":"The memristor has been identified as a potential solution for achieving non-von Neumann computation due to its ability to perform computation-in-memory, therefore bypassing the memory transfer bottleneck. Many memristive technologies have emerged with various mechanisms ranging from binary resistive switching to fully analog intercalation-based memristors. However, application of memristors to novel computing architectures have been mostly limited to memory arrays and multiply-and-accumulate functions, for example in convolutional neural networks (CNN) [1]. However, future recurrent neural networks (RNN) must implement complex temporal dynamics. Hence, a memristor model is proposed with the versatility to emulate various memristive technologies, including those with a true or virtual dependence on flux-linkage, as well as deploy temporal computation for the investigation of new computing architectures.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116858907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Yakar, B. Uzlu, Daniel S. Schneider, A. Grundmann, S. Becker, J. Niehaus, H. Schlicke, M. Heuken, H. Kalisch, A. Vescan, Zhenxing Wang, M. Lemme
{"title":"MoS2/Quantum Dot Hybrid Photodetectors on Flexible Substrates","authors":"O. Yakar, B. Uzlu, Daniel S. Schneider, A. Grundmann, S. Becker, J. Niehaus, H. Schlicke, M. Heuken, H. Kalisch, A. Vescan, Zhenxing Wang, M. Lemme","doi":"10.1109/DRC55272.2022.9855791","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855791","url":null,"abstract":"MoS2 is a semiconducting transition-metal dichalcogenide and an attractive candidate for optoelectronics and flexible electronics due to its strong excitonic interactions, low dark current (IDark) and high mechanical strength. Photo detectors (PDs) based on MoS2 have been demonstrated with high responsivities and low IDark [1]–[3]. However, long response times, often in the range of several seconds, severely limit their use for imaging applications. Hybrid structures made of MoS2 and colloidal quantum dots (CQDs) have been shown to improve the response times down to the ms range [4]. These devices were made from exfoliated materials and on rigid substrate. Here, we present hybrid MoS2/CQDs based PDs with high performance using a scalable fabrication approach on flexible polyimide (PI) substrates with metalorganic vapor phase epitaxy (MOVPE) grown MoS2. Our MoS2/CQDs PDs show fast response times in the ms range and withstand mechanical strain, which provides evidence that our scalable process on PI substrates is a promising approach towards flexible optoelectronics, e.g. wearable sensors or healthcare systems.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications","authors":"G. Galderisi, T. Mikolajick, J. Trommer","doi":"10.1109/DRC55272.2022.9855805","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855805","url":null,"abstract":"Reconfigurable Field Effect Transistors (RFETs) are, typically, multi-gated Schottky barrier (SB) FETs providing both unipolar n-type and p-type conduction mechanisms and polarity switching capabilities at runtime [1]. Three-gated RFETs (Fig. 1a) can provide such properties and enable a multi-VT behaviour [2]. The device polarity is always programmed by fixing a voltage at the program gate, that overlaps the device drain side Schottky junction. The high-V T mode can be triggered when the transistor is steered at both the other Schottky junction overlapping gate and the central one. The low-VT mode is enabled when the programming is performed at both junctions and only the central gate steers the channel (Fig. 1c), From a circuit perspective, these features enable the chance to dynamically reconfigure parts of a complex netlist to perform different tasks: the potential for an innovative functional scaling paradigm of new generations of nanoelectronic devices can be then unlocked. However, laboratory scale fabricated RFETs suffer from low yields, limited adaptability, and difficult control of challenging intermediate process steps, like silicidation [3].","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Demonstration of Patterned GaN RF MIS-HEMTs Growing on Hybrid Oriented Silicon-on-Insulator (SOI) Substrates","authors":"Bao-Yuan Wang, Chin-Ya Su, Tian-Li Wu","doi":"10.1109/DRC55272.2022.9855794","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855794","url":null,"abstract":"GaN HEMTs are promising for the RF applications due to the high electron mobility. Recently, GaN-on-Si technologies attracts lots of attentions. Furthermore, the SOI substrate is also promising for the RF applications due to the reduction of the substrate loss. However, the typical GaN-on-SOI (silicon-on-insulator) requires the epitaxy on top of the SOI substrates.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130153034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Free-Standing High Power GaN Multi-Fin Camel Diode Varactors","authors":"Po‐Chun Chen, P. Asbeck, S. Dayeh","doi":"10.1109/DRC55272.2022.9855653","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855653","url":null,"abstract":"To achieve wideband tunable filters that can handle high power in RF front end modules, high voltage varactors with a high quality factor, Q, are required. Among candidate semiconductor materials for high breakdown voltages exceeding 100V, gallium nitride (GaN) varactors can theoretically reach the highest figure of merit, Qmin, owing to outstanding breakdown field and good electron mobility1. However, high reverse bias leakage currents lower the breakdown voltage and restrict Q of conventional vertical GaN -based Schottky diodes due to (i) limited barrier heights attained on GaN, and (ii) leakage through threading dislocations. Furthermore, generally high contact resistance of p-type GaN Ohmic contact limits Q of vertical GaN pn junction diodes2, Here, we report devices that overcome these limitations by combining novel material and device architectures. First, we employ a camel diode structure composed of a thin and fully depleted p+ GaN top layer situated between the Schottky metal and an n-type GaN drift layer3. This raises the barrier height to suppress electron tunneling when compared to Schottky diodes (Fig. 1 a) and reduces the overlap of states for band-to-band tunneling in pn diodes. Second, we utilize GaN on a QST (Qromis Substrate Technology) wafer that permits the growth of thick GaN layers with lower dislocation densities and lower leakage than GaN-on-Si4. We report in this work the DC and s-parameter characterization results and discuss the potential of this varactor technology.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121057137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing","authors":"Saikat Chakraborty, J. Kulkarni","doi":"10.1109/DRC55272.2022.9855655","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855655","url":null,"abstract":"Recent advancements in cryogenic quantum computing technologies offer the promise to provide an exponential speedup for certain compute applications. Due to large number of arbitrary rotations required in a quantum algorithm and continuous error correction to preserve the data integrity, it requires extensive memory and bandwidth [1]. Using DRAM as main memory operational at 77K [1], can keep the cooling cost low while still providing significantly lower leakage along with larger capacity. Thanks to the denser bitcell footprint compared to the 1T-1C DRAM cells, capacitor-less single transistor DRAM (1T-DRAM) devices have been explored to construct scalable memory systems for cryogenic applications. Lowering the temperature improves the retention time of the 1 T DRAM cells by reducing the generation and recombination of carriers, a major retention failure mechanism of the 1 T DRAM cells [2] at higher temperatures. Recently, a cryogenic 1 T-DRAM cell has been demonstrated using a partially depleted silicon-on-insulator (PDSOI) n-MOSFET with a floating body [3]. However, the reported narrow cell current margin results in a slow read operation and quasi-destructive read operation can impact endurance. Since the impact ionization or GIDL effect is the major write mechanism for the cell, reported write speed is also slow (> 10ns). Capacitor-less DRAMs based on Thin Capacitively Coupled Thyristor (TCCT) benefits from a very large Ion/off current ratio (> 107) and a non-destructive read that enable a fast read/write speed (<2 ns) [4], [5]. A novel Floating Body Diode (FBD) memory was proposed [6] by Intel, which builds upon the same gated thyristor principle of operation in a FinFET form-factor making it scalable as well as a lower voltage memory. These unique features can enable a simple, logic compatible, high speed, and high density memory for cryogenic applications. However, device-circuit optimization studies of TCCT DRAMs specifically for cryogenic applications have been rather limited. In this paper, through TCAD simulations, a thyristor RAM (TRAM) is demonstrated for cryogenic applications for the first time.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117192401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Charnas, Jackson D. Anderson, J. Zhang, D. Zheng, D. Weinstein, P. Ye
{"title":"Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure","authors":"A. Charnas, Jackson D. Anderson, J. Zhang, D. Zheng, D. Weinstein, P. Ye","doi":"10.1109/DRC55272.2022.9855782","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855782","url":null,"abstract":"Ultra-thin indium oxide (In2O3) from several nanometers to sub-nanometer thick has recently been revealed as an excellent n-type semiconductor channel material for back-end-of-line (BEOL) compatible transistors due to its low thermal budget, low subthreshold swing (SS), high on current and Ion/Ioff ratio, and high mobility [1]–[3]. However, a critical question that has not yet been addressed is that of the maximum frequency at which these devices can operate, which will play a deciding role in their analog applications. This work reports for the first time the detailed radio frequency (RF) characterization of some of these In2O3 RF transistors scaling down to 150 nm channel lengths.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Joishi, N. K. Kalarickal, Wahidur Rahman, W. Lu, S. Rajan
{"title":"Ultra-Wide Bandgap Semiconductor Transistors for mm-wave Applications","authors":"C. Joishi, N. K. Kalarickal, Wahidur Rahman, W. Lu, S. Rajan","doi":"10.1109/drc55272.2022.9855796","DOIUrl":"https://doi.org/10.1109/drc55272.2022.9855796","url":null,"abstract":"This presentation will give an overview of the current status and future opportunities for high-frequency ultrawide bandgap (UWBG) semiconductor transistors. GaN-based transistors have demonstrated excellent performance for RF applications, but are close to the limits set by their electronic properties in the mm-wave regime. UWBG semiconductors such as high Al-content AlGaN can provide significantly higher breakdown electric field while having electron saturated velocity similar to GaN, and can in principle provide significant improvements in power-gain product at mm-wave frequencies. However, key challenges in real devices such as high contact resistance, premature breakdown of metal-semiconductor and dielectric interfaces, and thermal management must be addressed before such improved performance is realized.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127428407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}