Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation

Abstract

Multilevel cell (MLC) Resistive Random Access Memory (RRAM) is an attractive technology option to realize ultra-high density, low-power memory arrays [1]. Traditional 1-transistor 1-resistor (1T1R) bitc ell suffers from adjacent state overlap due to the inherent RRAM variations which hinders the realization of MLC capability [2]. In this work, we evaluate an alternate 2-transistor 1-resistor (2T1R) gain-cell RRAM bitcell topology that has higher read-out dynamic range and exhibits higher process variation tolerance compared to the baseline 1T1R bitcell [3]. We perform a thorough statistical estimation and variability analysis for both single-level cell (SLC) and MLC operation. For SLC operation, 2T1R can tolerate up to 400,70 higher RRAM variations than 1T1R and up to 200% higher variations for an iso-read power comparison. For MLC operation, it is 20-30% more variation tolerant and can provide the same robustness at lower read power. The write power of both bitcells is almost identical due to similar write mechanisms.