2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第3页

Implementation of FPGA-based Accelerator for Deep Neural Networks 基于fpga的深度神经网络加速器的实现

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724665

T. Tsai, Yuan-Chen Ho, M. Sheu

引用次数: 17

Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems 双vdd低功耗嵌入式数字系统的数字化管理电压域可编程机制

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724664

Ching-Hwa Cheng, Tang-Chieh Liu

{"title":"Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems","authors":"Ching-Hwa Cheng, Tang-Chieh Liu","doi":"10.1109/DDECS.2019.8724664","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724664","url":null,"abstract":"A built-in digitalized power management (DPMM) and voltage domain programmable (VDP) mechanisms are proposed to design a low-power system. In the proposed techniques, the high and low voltages applied to logic modules can be switchable. This flexible voltage-domain assignment allows the chip performance and power consumption can dynamically adjust during circuit operation. To support the DPMM and VDP mechanisms, the voltage-level monitor circuit and power-switch circuit are designed to support multiple operation modes for DPMM-VDP digital circuit designs. A powerless retention flip-flop is developed for temporary data storage during voltage domain dynamically switching. While to prevent the system failure come from voltage integrity problem, a built-in voltage-level monitoring mechanism is utilized to monitor voltage integrity during VDP circuit operation. The proposed mechanism allows the chip performance and power consumption to be flexibly adjusted during circuit operation. The physical implementation chips and measured results proof of this methodology has $30 sim 55$% power reduction comparisons with using single-Vdd.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134397477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High side power MOSFET switch driver for a low-power AC/DC converter 用于低功率AC/DC变换器的高侧功率MOSFET开关驱动器

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724667

M. Potocný, J. Brenkus, V. Stopjaková

引用次数: 2

Hash-based Pattern Matching for High Speed Networks 高速网络中基于哈希的模式匹配

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724652

Tomás Fukac, J. Korenek

{"title":"Hash-based Pattern Matching for High Speed Networks","authors":"Tomás Fukac, J. Korenek","doi":"10.1109/DDECS.2019.8724652","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724652","url":null,"abstract":"Regular expression matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links and the number of regular expressions, pattern matching architectures have to be improved to retain wire-speed processing. Multi-striding is a well-known technique to increase processing speed but it requires a lot of FPGA resources. Therefore, we focus on the design of new hardware architecture for fast pre-filtering of network traffic. The proposed pre-filter performs fast hash-based matching of short strings, which are specific for matched regular expressions. As the proposed pre-filter significantly reduces input traffic, exact pattern matching can operate on significantly lower speeds. Then the exact pattern match can be done by CPU or by a slow automaton with a few hardware resources. The paper provides analyses of false-positive detection of the pre-filter with respect to the length of matching strings. The number of false-positives is low, even if the length of the selected strings is short. Therefore input traffic can be significantly reduced. For 100 Gb links, the pre-filter reduced the input data to 1.83 Gbps using four-symbol strings.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121675702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

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2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/ddecs.2019.8724666

引用次数: 0

A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider 一种5至10.5 GHz低功耗宽带I/Q发射机，集成电流模式逻辑分频器

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724638

H. Chiou, Wei-Min Sung

引用次数: 1

A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System 基于深度学习模型的草图分类器技术在嵌入式系统中的实现

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724656

T. Tsai, Po-Ting Chi, Kuo-Hsing Cheng

引用次数: 4

Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic 用于加密网络流量实时分析的特征提取加速

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724658

R. Vrána, J. Korenek, David Novak

引用次数: 1

Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime 考虑电路收敛的可测试性措施以减少ATPG运行时间

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724660

Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang

引用次数: 4

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers 高吞吐量级联分类器的体系结构感知内存访问调度

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724671

Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen

{"title":"Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers","authors":"Hsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen","doi":"10.1109/DDECS.2019.8724671","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724671","url":null,"abstract":"Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124330358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1