2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test 结合老化和系统级测试有效筛选汽车soc

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724644

F. Almeida, P. Bernardi, D. Calabrese, Marco Restifo, M. Reorda, D. Appello, G. Pollaccia, V. Tancorre, R. Ugioli, G. Zoppi

{"title":"Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test","authors":"F. Almeida, P. Bernardi, D. Calabrese, Marco Restifo, M. Reorda, D. Appello, G. Pollaccia, V. Tancorre, R. Ugioli, G. Zoppi","doi":"10.1109/DDECS.2019.8724644","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724644","url":null,"abstract":"Automotive systems must reach a high reliability in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible defects that could manifest during lifetime. Burn-In (BI) is a manufacturing test phase used for screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing process of complex Systems on Chip (SoCs) mimicking the operational conditions. This paper aims at describing the motivations for and the effectiveness stemming from combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. Moreover, the paper analyses the required tester architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics is used to demonstrate the possible cost reduction.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116664483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Fault-Aware Performance Assessment Approach for Embedded Networks 嵌入式网络的故障感知性能评估方法

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724670

Jan Malburg, Karl Janson, J. Raik, F. Dannemann

引用次数: 0

New categories of Safe Faults in a processor-based Embedded System 基于处理器的嵌入式系统安全故障的新分类

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724642

C. C. Gürsoy, M. Jenihhin, Adeboye Stephen Oyeniran, D. Piumatti, J. Raik, M. Reorda, R. Ubar

引用次数: 3

Hardware and control design of a ball balancing robot 球平衡机器人的硬件及控制设计

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724645

Ioana Lal, Marius Nicoara, A. Codrean, L. Buşoniu

引用次数: 1

Generic Error Localization for the Electronic System Level 电子系统级通用错误定位

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724637

S. Pointner, Pablo González de Aledo Marugán, R. Wille

引用次数: 0

Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI’s Components using RAD-THERM TCAD Subsystem 基于RAD-THERM TCAD子系统的BiCMOS LSI元件辐射和温度诱导故障建模与仿真

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724651

K. Petrosyants, M. Kozhukhov, Dmitry Popov

引用次数: 1

Automated Integration of Dynamic Power Management into FPGA-Based Design 动态电源管理与fpga设计的自动化集成

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724635

M. Skuta, Dominik Macko

{"title":"Automated Integration of Dynamic Power Management into FPGA-Based Design","authors":"M. Skuta, Dominik Macko","doi":"10.1109/DDECS.2019.8724635","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724635","url":null,"abstract":"A low power or energy efficient hardware operation is nowadays gaining attention. It is especially true for battery-operated or energy-harvesting devices, such as most of the Internet of Things end nodes. For specific applications with rather limited market, the FPGAs are very good alternative. However, evolution of these devices is focused on high-level programming, giving application designers space to focus on application function rather than to be concerned about its low-level implementation on FPGA device – it is handled by automation tools. Thus, new FPGA-application designers are nowadays not very familiar with hardware aspects and it is difficult for them to apply power-reduction techniques in order to create an energy-efficient system. This paper is focused on automation of power-management integration into the FPGA-application design based on abstract specification, which is easy-to-use even for unfamiliar designers. It simplifies and speeds-up the low-power and energy-efficient FPGA-application design process. Moreover, the automation prevents many human-errors and thus it also alleviates the verification process. Experimental results indicate that the proposed power-management scheme is working correctly and it can be automatically generated.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127109208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

On the in-field test of the GPGPU scheduler memory GPGPU调度器内存的现场测试

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724672

S. Carlo, J. E. R. Condia, M. Reorda

{"title":"On the in-field test of the GPGPU scheduler memory","authors":"S. Carlo, J. E. R. Condia, M. Reorda","doi":"10.1109/DDECS.2019.8724672","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724672","url":null,"abstract":"GPGPUs have been increasingly successful in the past years in many application domains, due to their high parallel processing capabilities and energy performance. More recently, they started to be used in areas (such as automotive) where safety is also an important parameter. However, their architectural complexity and advanced technology level create challenges when matching the required reliability targets. This requires devising solutions to perform in-field test, thus allowing the systematic detection of possible permanent faults. These faults are caused by aging or external factors that affect the application execution and potentially generate critical misbehaviors. Moreover, effective in-field test techniques oriented to verify the integrity of GPGPU modules during in-field operation are still missed. In this work, we propose a method to generate self-test procedures able to detect all static faults affecting the scheduler memory existing in each streaming multiprocessor (SM) of a GPGPU. NVIDIA CUDA-C is selected as high-level programing language. The experimental results are obtained employing the NVIDIA Nsight Debugger on a NVIDIA-GEFORCE GTX GPU and a memory fault simulator.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123997097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Nonlinear Compression Codes Used In IC Testing 用于集成电路测试的非线性压缩码

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724661

O. Novák

引用次数: 1

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing 基于在线应用测试的mpsoc硬件木马检测与恢复

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724649

Amin Malekpour, R. Ragel, Daniel Murphy, A. Ignjatović, S. Parameswaran

{"title":"Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing","authors":"Amin Malekpour, R. Ragel, Daniel Murphy, A. Ignjatović, S. Parameswaran","doi":"10.1109/DDECS.2019.8724649","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724649","url":null,"abstract":"We present a Hardware Trojan (HT) detection, identification and recovery mechanism for Multiprocessor Systems on Chips (MPSoCs). Our method utilizes on-line testing to mitigate the effects of hardware Trojans in a computing system using a Hardware Security Monitor (HSM), a trusted hardware module, and an On-line Test Procedure (OTP), a software module. The proposed approach focuses on mitigating hardware Trojans with a permanent impact on the computing system and enables MPSoCs to continue functioning in the presence of the hardware Trojans. We have successfully validated the proposed method by implementing known hardware Trojans from Trust-Hub on a Xilinx ML605 FPGA. The implementation incurred 4.5% area and 9.1% execution time overheads for a set of benchmark applications. Compared to the state of the art, the proposed mechanism’s area and power overheads are significantly lower while the execution time overhead is slightly higher. State of the art systems utilizing differing cores have been shown to be effective in simulation environments, while the proposed mechanism has been implemented in FPGAs to illustrate that such a system can be realized in hardware.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0