2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第2页

A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network 基于fpga的PCBA配电网杂散变化检测新方法

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-24 DOI: 10.1109/DDECS.2019.8724662

S. Odintsov, Ludovica Bozzoli, C. D. Sio, L. Sterpone, A. Jutman

{"title":"A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network","authors":"S. Odintsov, Ludovica Bozzoli, C. D. Sio, L. Sterpone, A. Jutman","doi":"10.1109/DDECS.2019.8724662","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724662","url":null,"abstract":"Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA)with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various subsystems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hybrid on-line self-test architecture for computational units on embedded processor cores 嵌入式处理器核上计算单元的混合在线自检体系结构

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-16 DOI: 10.1109/DDECS.2019.8724647

A. Floridia, Gianmarco Mongano, D. Piumatti, E. Sánchez

{"title":"Hybrid on-line self-test architecture for computational units on embedded processor cores","authors":"A. Floridia, Gianmarco Mongano, D. Piumatti, E. Sánchez","doi":"10.1109/DDECS.2019.8724647","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724647","url":null,"abstract":"Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Using Voters May Lead to Secret Leakage 利用选民可能导致秘密泄露

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724663

Jan Belohoubek, P. Fiser, Jan Schmidt

引用次数: 4

Encryption-Based Secure JTAG 加密安全JTAG

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724654

E. Valea, M. D. Silva, M. Flottes, G. D. Natale, B. Rouzeyre

引用次数: 6

DDECS 2019 Foreword

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/ddecs.2019.8724655

引用次数: 0

FPGA-based SIFT implementation for wearable computing 基于fpga的可穿戴计算SIFT实现

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724653

Attila Fejér, Z. Nagy, J. Benois-Pineau, P. Szolgay, A. Rugy, J. Domenger

引用次数: 4

Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines 转底炉检修机容错控制系统

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724648

V. Muresan, M. Abrudean

引用次数: 2

DDECS 2019 Sponsors

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/ddecs.2019.8724640

引用次数: 0

Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology 130纳米CMOS技术的超低电压轨对轨比较器设计

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724650

L. Nagy, D. Arbet, M. Kovác, M. Potocný, V. Stopjaková

引用次数: 5

Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts 开发可穿戴硬件平台，利用IMU测量心电和肌电，检测运动伪影

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724639

M. Tanweer, K. Halonen

{"title":"Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts","authors":"M. Tanweer, K. Halonen","doi":"10.1109/DDECS.2019.8724639","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724639","url":null,"abstract":"Weareable biomedical devices make it possible to monitor physiological parameters of human beings where physical fitness is critical for their work. However, the motion artifacts corrupt the ambulatory measurements of electrophysiological parameters and it is necessary to detect and eliminate these motion artifacts. The long term measurement and analysis of health parameters require enormous data processing and storage resources on board. It is also challenging to perform sensor fusion of multiple devices and to manage multiple communication channels. This paper describes the development of a wearable hardware platform to measure electrocardiogram (ECG) and electromyogram (EMG) with an additional IMU sensor to detect the motion artifacts. Bringing all the sensors on single platform resolves the sensor fusion problems. The measurements are digitized and sent wirelessly through a bluetooth interface to a remote unit in real-time. Which is capable for the implementation of extensive processing and analysis algorithms to detect the motion artifacts and extract The features of ECG and EMG waveform structures.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117111934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10