FPGA-based SIFT implementation for wearable computing

The article describes the first steps to achieve control over a robotic or prosthetic arm based on analysis of visual environment acquired in real-time by video cameras on glasses and on the prosthesis. One of the main goals of the research is to develop a wearable, portable, lightweight, and low power consumption device for visual scene analysis. This paper will discuss the critical steps of its implementation on an FPGA board. We implemented some time-consuming parts of the SFT algorithm needed for the analysis in C/C++ language on TUL PYNQ-Z2 FPGA board. This implementation allows for a low power consumption of the programmable logic part of the system. The obtained value is 0. 274W. Processing capacity is 96.45 images per second on a small wearable size device which allow for the real-time implementation of the whole analysis in the future.