2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第4页

Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology 基于寄生感知设计方法的低压亚阈值电荷泵研究

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724668

M. Kovác, D. Arbet, V. Stopjaková, Michal Sovcík, L. Nagy

引用次数: 2

[DDECS 2019 Breaker page] [DDECS 2019断路器页面]

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/ddecs.2019.8724631

引用次数: 0

Modular Data Link Layer Processing for THz communication 太赫兹通信的模块化数据链路层处理

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724657

L. Lopacinski, M. Eissa, G. Panic, A. Hasani, R. Kraemer

引用次数: 0

Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter 基于增加抖动低功率振荡器的真随机数发生器设计

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724643

Mariusz Derlecki, Krzysztof Siwiec, Paweł Narczyk, W. Pleskacz

引用次数: 0

From Constraints to Tape-Out: Towards a Continuous AMS Design Flow 从约束到纸带:走向连续的AMS设计流程

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724669

Andreas Krinke, T. Horst, G. Glaeser, Martin Grabmann, Tobias Markus, Benjamin Prautsch, U. Hatnik, J. Lienig

引用次数: 1

Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems 硬实时和混合临界系统的低延迟硬件加速动态内存管理器

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724659

L. Kohútka, L. Nagy, V. Stopjaková

{"title":"Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems","authors":"L. Kohútka, L. Nagy, V. Stopjaková","doi":"10.1109/DDECS.2019.8724659","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724659","url":null,"abstract":"This paper presents a novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations. Due to very low and constant latency of these operations with respect to the actual number and location of free blocks of memory, the proposed solution is suitable for hard real-time and mixed-criticality systems. The proposed hardware-accelerated memory manager implements Worst-Fit algorithm for selection of a suitable free block of memory that can be used by the external environment, e.g. CPU or any custom hardware. The proposed solution uses hardware-accelerated max queue, which is a data structure that continuously provides the largest free memory block in two clock cycles regardless of the actual number or constellation of available free blocks. The proposed memory manager was verified using simplified version of UVM and applying billions of randomly generated instructions as test inputs. A synthesis into Intel FPGA Cyclone V was performed, and the synthesis results are presented as well. The memory manager was also synthesized into 28 nm technology with 1 GHz clock frequency and the power supply voltage of 0.9 V. The ASIC synthesis results show that the proposed memory manager consumes additional chip area from 35% to 70% of the managed memory.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132169635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430 软核处理器NEO430运行时可重构容错体系结构

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724636

Karel Szurman, Z. Kotásek

{"title":"Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430","authors":"Karel Szurman, Z. Kotásek","doi":"10.1109/DDECS.2019.8724636","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724636","url":null,"abstract":"Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by the cosmic radiation. Therefore, SEU mitigation strategy is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and thus, to perform implemented functionality after the occurrence of a fault. In this paper, we propose a run-time reconfigurable FT architecture based on coarse-grained TMR with triplicated soft-core processor NEO430 core, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when the reconfiguration of a failed processor instance was finished into the state where all three processors operate synchronously. The paper describes implemented FT architecture and run-time fault recovery strategy performing all necessary steps without additional blocking of the system functionality. The state synchronization for the soft-core processor NEO430 architecture is described in a further detail. Moreover, the paper presents developed PDR framework used for validation and testing of proposed fault recovery strategy.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128393690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DDECS 2019 Committees DDECS 2019委员会

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/ddecs.2019.8724633

引用次数: 0

Analyzing and Optimizing the Dummy Rounds Scheme 仿真弹方案的分析与优化

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI: 10.1109/DDECS.2019.8724632

Stanislav Jerabek, Jan Schmidt

引用次数: 4