Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems

Abstract

A built-in digitalized power management (DPMM) and voltage domain programmable (VDP) mechanisms are proposed to design a low-power system. In the proposed techniques, the high and low voltages applied to logic modules can be switchable. This flexible voltage-domain assignment allows the chip performance and power consumption can dynamically adjust during circuit operation. To support the DPMM and VDP mechanisms, the voltage-level monitor circuit and power-switch circuit are designed to support multiple operation modes for DPMM-VDP digital circuit designs. A powerless retention flip-flop is developed for temporary data storage during voltage domain dynamically switching. While to prevent the system failure come from voltage integrity problem, a built-in voltage-level monitoring mechanism is utilized to monitor voltage integrity during VDP circuit operation. The proposed mechanism allows the chip performance and power consumption to be flexibly adjusted during circuit operation. The physical implementation chips and measured results proof of this methodology has $30 \sim 55$% power reduction comparisons with using single-Vdd.