{"title":"A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider","authors":"H. Chiou, Wei-Min Sung","doi":"10.1109/DDECS.2019.8724638","DOIUrl":null,"url":null,"abstract":"This paper presents a 5-10.5 GHz wideband fully-integrated I/Q transmitter in tsmc™ 90-nm CMOS technology. A current-mode passive mixer was adopted to enhance the linearity and low-power performance. The transmitter also integrated current-mode logic (CML) frequency divider (FD) to generate I/Q signals at LO-port. The I/Q signals were directly combined by using high-Q top-metal lines. An inductively coupled resonator (ICR) wideband output matching network was used to transform balance to unbalance output signal in RF drive-amplifier. The proposed transmitter achieves a 3-dB bandwidth from 5 to 10.5 GHz, a conversion gain of 12.9 dB, an output P1dB of -4.17 dBm, an output IP3 of 16.47 dBm, a carrier suppression of 30.02 dBc and a sideband suppression of 39.62 dBc under an LO power of 14 dBm at the center frequency of 8 GHz. The chip consumed dc power of 66.36 mW. The chip dimensions, including all RF and DC pads, are 1.25 × 1.1 mm2.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"3 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2019.8724638","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a 5-10.5 GHz wideband fully-integrated I/Q transmitter in tsmc™ 90-nm CMOS technology. A current-mode passive mixer was adopted to enhance the linearity and low-power performance. The transmitter also integrated current-mode logic (CML) frequency divider (FD) to generate I/Q signals at LO-port. The I/Q signals were directly combined by using high-Q top-metal lines. An inductively coupled resonator (ICR) wideband output matching network was used to transform balance to unbalance output signal in RF drive-amplifier. The proposed transmitter achieves a 3-dB bandwidth from 5 to 10.5 GHz, a conversion gain of 12.9 dB, an output P1dB of -4.17 dBm, an output IP3 of 16.47 dBm, a carrier suppression of 30.02 dBc and a sideband suppression of 39.62 dBc under an LO power of 14 dBm at the center frequency of 8 GHz. The chip consumed dc power of 66.36 mW. The chip dimensions, including all RF and DC pads, are 1.25 × 1.1 mm2.