考虑电路收敛的可测试性措施以减少ATPG运行时间

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2019-04-01 DOI:10.1109/DDECS.2019.8724660

Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang

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引用次数: 4

摘要

再收敛已被认为是ATPG回溯的主要原因。它不仅会导致更多的回溯，而且还会导致比预期更严重的性能下降。在本文中，我们提出了一个再收敛感知的可测试性度量，以更好地指导ATPG的论证过程。实验结果表明，该方法显著降低了ATPG运行时间，特别是对于具有深层逻辑电平的电路，运行时间可达76%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime

Reconvergence has been recognized as the main reason for ATPG backtrack. It induces not only more, but also prolonged backtracks and causes more severe performance degradation than expected. In this paper, we propose a reconvergence-aware testability measure to better guide the ATPG justification process. Experiment results show that the proposed method significantly decreases the ATPG runtime, especially for circuits with deep logic level, by up to 76%.

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来源期刊

2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

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