2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第8页

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead 结合未指定测试数据位填充方法和基于运行长度的代码来估计压缩、功率和面积开销

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.18

U. Mehta, N. Devashrayee, K. Dasgupta

引用次数: 7

System Level Design for Embedded Reconfigurable Systems Using MORPHEUS Platform 基于MORPHEUS平台的嵌入式可重构系统的系统级设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.13

Paul Brelet, Arnaud Grasset, P. Bonnot, F. Ieromnimon, D. Kritharidis, N. Voros

引用次数: 4

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration 基于局部和动态重构的FPGA快速顺序启动

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.19

M. Hübner, Joachim Meyer, O. Sander, L. Braun, J. Becker, Juanjo Noguera, Rodney Stewart

{"title":"Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration","authors":"M. Hübner, Joachim Meyer, O. Sander, L. Braun, J. Becker, Juanjo Noguera, Rodney Stewart","doi":"10.1109/ISVLSI.2010.19","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.19","url":null,"abstract":"Due to their their high flexibility and their increasing logic resources, FPGAs can be found in a wider application range as in recent years. But especially in application domains, where only a very restricted power budget is available, FPGAs still have to compete with other solutions. To reduce the power consumption to a minimum, many devices use different kinds of power saving modes, called sleep modes. In those modes they sacrifice functionality for the benefit of a lower consumption. Taking this idea to the extreme, many devices are only powered when it is necessary. If not, they are released from their power supply and do not drain current at all. The realization of such a sleep mode for a SRAM-based FPGA leads to difficulties. This is caused due to the fact, that the volatile memory is used to save the configuration of the device. The configuration has to be reloaded into the device every time when reattaching the power to the FPGA. This circumstance leads to restrictions for the device deployment in some electronic systems since in many cases the time a device may use to wake up is strictly limited. In several use cases, the configuration time of a SRAM based FPGA exceeds this limitation. This paper describes to decrease the configuration time of a design by exploiting the method of dynamic and partial reconfiguration in order to enable the usage of a sleep mode. With the presented method, the configuration time of any Xilinx SRAM based FPGA from the identical series (e.g. Spartan) is independent from the size of the used device.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115279542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A New Low-Power Soft-Error Tolerant SRAM Cell 一种新型低功耗软容错SRAM单元

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.83

N. Axelos, K. Pekmestzi, N. Moschopoulos

引用次数: 4

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array TRB:标签复制缓冲区，用于提高缓存标签阵列的可靠性

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.25

Shuai Wang, Jie S. Hu, Sotirios G. Ziavras

{"title":"TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array","authors":"Shuai Wang, Jie S. Hu, Sotirios G. Ziavras","doi":"10.1109/ISVLSI.2010.25","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.25","url":null,"abstract":"Protecting the on-chip cache memories against soft errors has become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have mainly focused on improving the reliability of the cache data arrays. Due to its crucial importance to the correctness of cache accesses, the tag array demands high reliability against soft errors while the data array is fully protected. Exploiting the address locality of memory accesses, we propose to duplicate most recently accessed tag entries in a small Tag Replication Buffer (TRB) thus to protect the information integrity of the tag array in the data cache with low performance, energy and area overheads. A Selective-TRB scheme is further proposed to protect only tag entries of dirty cache lines. The experimental results show that the Selective-TRB scheme achieves a higher access-with-replica (AWR) rate of 97.4% for the dirty-cache line tags. To provide a comprehensive evaluation of the tag-array reliability, we also conduct an architectural vulnerability factor (AVF) analysis for the tag array and propose a refined metric, detected-without-replica-AVF (DOR-AVF), which combines the AVF and AWR analysis. Based on our DOR-AVF analysis, a TRB scheme with early write-back (EWB) is proposed, which achieves a zero DOR-AVF at a negligible performance overhead.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130315172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Exploration of 2D Cellular Automata as Binary Sequence Generators 二维元胞自动机作为二进制序列发生器的探索

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.34

E. Arvaniti, Ilias Mavridis, A. Kakarountas

引用次数: 3

Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform VLSI中的自主设计:一个内部通用细胞神经平台

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.29

L. Krundel, D. Mulvaney, V. Chouliaras

引用次数: 2

Task Dispersal Measurement in Dynamic Reconfigurable NoCs 动态可重构noc中的任务分散度量

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.91

Mohammad Hosseinabady, J. Núñez-Yáñez, A. Coppola

引用次数: 1

A Family of Area-Time Efficient Modulo 2n+1 Adders 一类面积-时间有效模2n+1加法器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.35

H. T. Vergos

引用次数: 5

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture 一种具有子Flash架构的新型可变分辨率Flash ADC

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.68

M. K. Adimulam, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas

引用次数: 7