2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第7页

Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing 基于fpga自适应计算的进程间通信管道

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.103

Ming Liu, Zhonghai Lu, W. Kuehn, A. Jantsch

引用次数: 10

Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays 恢复增强:一种增强SRAM阵列NBTI恢复的技术

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.15

Taniya Siddiqua, S. Gurumurthi

{"title":"Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays","authors":"Taniya Siddiqua, S. Gurumurthi","doi":"10.1109/ISVLSI.2010.15","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.15","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is always in the negative bias condition at any given time. In this paper, we propose a technique called Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery mode by slightly modifying the design of conventional SRAM cells. We present the circuit-level design of an issue queue that uses such cells and perform SPICE-level simulations to verify its functionality and quantify area and power consumption. We then conduct an architecture-level evaluation of the performance and reliability of using an area-neutral design of such an issue queue using the M5 simulator and the SPEC CPU2000 benchmark suite. We show that recovery boosting provides a 56% improvement in the static noise margin for the issue queue while having very little impact on power consumption and a negligible loss in performance.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits Testing 基于FGMOS的内置电流传感器用于低电压模拟和混合信号电路测试

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.31

S. Siskos

引用次数: 8

The Impact of Process Faults on Specific Parameters of a 1.9GHz CMOS Mixer 工艺故障对1.9GHz CMOS混频器特定参数的影响

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.55

A. Karagounis, B. Kotsos, N. Assimakis, E. Petropoulou, A. Polyzos

引用次数: 0

A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd 一种针对多Vdd的3D NoC架构的高级映射算法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.98

K. Siozios, Iraklis Anagnostopoulos, D. Soudris

引用次数: 12

Dynamic Power Management on LDPC Decoders LDPC解码器的动态电源管理

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.70

E. Amador, R. Knopp, V. Rezard, R. Pacalet

引用次数: 12

High-Performance TSV Architecture for 3-D ICs 3-D集成电路的高性能TSV架构

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.24

M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen

引用次数: 4

Hybrid QoS Method for Networks-on-Chip 片上网络的混合QoS方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.12

Shijun Lin, Jianghong Shi, Huihuang Chen

引用次数: 1

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching 结合穷举搜索和基于梯度的剪枝搜索的高效高级综合探索方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.56

S. Xydis, C. Skouroumounis, K. Pekmestzi, D. Soudris, G. Economakos

引用次数: 21

A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency 利用代码粒度在scratchpad提高能源效率的后编译方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.66

D. Volpato, Alexandre K. I. Mendonça, L. Santos, José Luís Almada Güntzel

{"title":"A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency","authors":"D. Volpato, Alexandre K. I. Mendonça, L. Santos, José Luís Almada Güntzel","doi":"10.1109/ISVLSI.2010.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.66","url":null,"abstract":"Since most of the energy spent in embedded processors is consumed when accessing instruction and data caches, scratchpad memories (SPMs) are promising for energy efficiency, because they require less energy per access than caches do. Most SPM mapping techniques require the availability of source code and are therefore unable to treat third-party software. This work handles precompiled software while simultaneously mapping code and data elements into SPMs. It evaluates energy savings for code elements defined either by procedure or basic block (BB) boundaries. For a subset of the MiBench program suite, the experimental results show that the adoption of BB boundaries leads to average energy savings of 30% for a 1KB SPM, which are 10% better than when procedure boundaries are considered. For procedure boundaries to achieve average energy savings comparable to those obtained with BBs, SPM size must be increased to 4KB, resulting in a 31% area overhead in the memory subsystem. Higher savings, on the order of 40%, were achieved for real-life use cases exhibiting BBs with high profit/cost ratios. This work also shows that, when exploiting the finer-grain BB boundaries to achieve higher savings, relocatable object files are the most efficient binary media (average patching time is 2.05 seconds), despite the higher number of resulting code elements (mapping takes at most 10 ms).","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7