2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第6页

Fast Evaluation of Analog Circuits Using Linear Programming 基于线性规划的模拟电路快速评估

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.94

Zachary Cashero, Allen Chen, Ryan Hoppal, Tom Chen

引用次数: 5

An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs 基于人工神经网络的noc热点预测机制

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.50

E. Kakoulli, V. Soteriou, T. Theocharides

{"title":"An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs","authors":"E. Kakoulli, V. Soteriou, T. Theocharides","doi":"10.1109/ISVLSI.2010.50","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.50","url":null,"abstract":"Hotspots are network on-chip (NoC) routers or modules in systems on-chip (SoCs) which occasionally receive packetized traffic at a rate higher than they can consume it. This adverse phenomenon greatly reduces the performance of an NoC, especially in the case of today’s widely-employed wormhole flow-control, as backpressure can cause the buffers of neighboring routers to quickly fill-up leading to a spatial spread in congestion that can cause the network to saturate. Even worse, such situations may lead to deadlocks. Thus, a hotspot prevention mechanism can be greatly beneficial, as it can potentially enable the interconnection system to adjust its behavior and prevent the rise of potential hotspots, subsequently sustaining NoC performance and efficiency. Unfortunately, hotspots cannot be known a-priori in NoCs used in general-purpose systems as application demands are not predetermined unlike in application-specific SoCs, making hotspot prediction and subsequently prevention difficult. In this paper we present an artificial neural network-based hotspot prediction mechanism that can be potentially used in tandem with a hotspot avoidance mechanism for handling an unforeseen hotspot formation efficiently. The network uses buffer utilization statistical data to dynamically monitor the interconnect fabric, and reactively predicts the location of an about to-be-formed hotspot, allowing enough time for the system to react to these potential hotspots. The neural network is trained using synthetic traffic models, and evaluated using both synthetic and real application traces. Results indicate that a relatively small neural network can predict hotspot formation with accuracy ranges between 76% to 92% when evaluated on two different mesh NoCs.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131281407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Input-Output Selection Based Router for Networks-on-Chip 基于输入输出选择的片上网络路由器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.76

M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen

引用次数: 9

Differential Power Analysis of CAST-128 CAST-128的差分功率分析

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.14

K. Boey, Yingxi Lu, Máire O’Neill, Roger Francis Woods

{"title":"Differential Power Analysis of CAST-128","authors":"K. Boey, Yingxi Lu, Máire O’Neill, Roger Francis Woods","doi":"10.1109/ISVLSI.2010.14","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.14","url":null,"abstract":"Power analysis is used to reveal the secret key of security devices by monitoring the power consumption of certain cryptographic algorithm operations through a statistical analysis approach known as Differential Power Analysis (DPA). Whilst this has been applied extensively to attacks on FPGA devices, there has been little research into attacks on ASIC devices. Although standard DPAs are essentially independent of the block cipher that they target, some are less susceptible than others due to algorithm’s structure, and therefore more difficult to attack such as the CAST-128. In this paper, we outline the first reported power analysis attack of CAST-128 as it falls into the category just outlined and it is the only algorithm that has not been practically broken either on FPGA or ASIC, it is also a common block cipher used in Canada. The paper outlines an approach that reveals all 128 bits of the secret key within 300,500 power traces, highlighting insights on attacking the registers rather than the Sbox. Finally, the effect of applying the Hamming weight power model on different widths of the target register under attack in ASIC device is evaluated.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation 亚阈值差分放大器直流偏置建模与噪声最小化

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.46

Kapil K. Rajput, Anil K. Saini, S. C. Bose

引用次数: 5

A High Throughput Low Power FIFO Used for GALS NoC Buffers 用于GALS NoC缓冲器的高吞吐量低功耗FIFO

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.44

Mohammad Fattah, Abdurrahman Manian, A. Rahimi, S. Mohammadi

引用次数: 19

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach 可扩展多核架构的映射优化:MOSART方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.71

B. Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, J. Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, Andreas Wiefrink, B. Vanthournout, Philippe Martin

{"title":"Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach","authors":"B. Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, J. Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, Andreas Wiefrink, B. Vanthournout, Philippe Martin","doi":"10.1109/ISVLSI.2010.71","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.71","url":null,"abstract":"The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays 一种网格连接处理器阵列的片上互连拓扑

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.86

Xiaofang Wang

引用次数: 3

BLAS Comparison on FPGA, CPU and GPU FPGA、CPU和GPU的BLAS比较

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.84

S. Kestur, John D. Davis, Oliver Williams

引用次数: 177

QCA Systolic Matrix Multiplier 收缩矩阵乘数

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.53

Liang Lu, Weiqiang Liu, Máire O’Neill, E. Swartzlander

引用次数: 21