A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays

Abstract

Prior studies on packet-switching on-chip networks have primarily focused on the micro architecture of the router to reduce the communication latency. In this paper, we propose a novel interconnection topology for mesh-connected processor arrays. By sharing routers among PEs and PEs among routers, our network significantly reduces the average hop count for a packet, thereby reducing the network latency and improving the throughput of the network. The interconnection network also requires less area compared to the conventional mesh organization, leaving more resources for the computing fabric. Extensive simulation results show that the proposed network reduces the network latency by up to 50.3 for a multiprocessor with 64 PEs.