2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第10页

A Hierarchical Hybrid Optical-Electronic Network-on-Chip 一种分层混合光电子片上网络

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.17

M. K. Hung, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu

引用次数: 74

BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels BBVC-3D-NoC:一种使用双向双同步垂直通道的高效3D NoC架构

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.21

A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen

引用次数: 14

Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars 可重构纳米尺度横梁设计映射中的缺陷与变异问题

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.43

B. Ghavami, A. Tajary, Mohsen Raji, H. Pedram

引用次数: 13

Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA 基于sram的FPGA的主从TMR容错技术

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.38

Farid Lahrach, A. Doumar, E. Châtelet, A. Abdaoui

引用次数: 10

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures 多核体系结构的并行范式和运行时管理技术

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.93

C. Silvano, W. Fornaciari, S. Crespi-Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. D. Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout

引用次数: 18

Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory 基于博弈论的动态能量管理方法实现分析

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.61

I. Mansouri, Camille Jalier, F. Clermidy, P. Benoit, L. Torres

引用次数: 5

A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing 用于生物医学信号处理的可重构智能ADC校准电路

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.85

S. Mostafa, W. Qu, S. Islam, M. Mahfouz

{"title":"A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing","authors":"S. Mostafa, W. Qu, S. Islam, M. Mahfouz","doi":"10.1109/ISVLSI.2010.85","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.85","url":null,"abstract":"Reconfigurable analog-to-digital converters (ADC) have been receiving increased attention in the research community for the capability to adapt to continuously varying signal processing requirements. The reconfigurable ADC is particularly advantageous in implantable biomedical sensor signal processing systems that processes signal in different range of frequency and amplitude levels and has low power consumption constraints. In this work a calibration circuit is presented that analyses the input signal from biomedical sensors and based on the dynamic range and frequency of the signal generates a two-bit control signal to change the configuration of the ADC for optimum resolution and power consumption. The two-bit control signal reconfigures the 10-bit 40MSPS pipeline ADC to operate in four different configurations by changing resolution, sampling clock and bias current for optimized operation. The calibration circuit is designed in 90 nm process and requires only 36.9μA current with 1V power supply and occupies 0.0054mm2 chip area. The reconfigurable ADC is designed in a 0.35 μm bulk CMOS process occupying 1.9mm2 area and consumes 35.4mW power in maximum performance configuration and 7.9mW in minimum power consumption configuration.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131449763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder H.264/SVC编码器的高效转换模块解决方案

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.87

R. Husemann, M. Majolo, A. Susin, V. Roesler, J. V. D. Lima

引用次数: 9

An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division 基于整数除法的8位电压模模数转换器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.27

N. Petrellis, M. Birbas, J. Kikidis, A. Birbas

引用次数: 3

An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip 片上网络有界偏转自适应路由的分析框架

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.90

P. Ghosh, Arvind Ravi, Arunabha Sen

{"title":"An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip","authors":"P. Ghosh, Arvind Ravi, Arunabha Sen","doi":"10.1109/ISVLSI.2010.90","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.90","url":null,"abstract":"In a Multi-Processor System-on-Chip (MPSoC)-based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components of NoC. Simulation based studies are time-consuming and do not provide adequate insight into the design parameters for performance improvement. In this paper, we provide a framework for the analytical study of the NoC components and design an adaptive routing algorithm. Based on the traffic pattern of the communication traffic among PEs, we perform analytical studies based on network calculus and probabilistic analysis. Analytical study relates the design parameters with the worst case and average case latency and buffer requirements. Knowledge obtained from the analytical study is utilized for resource allocation of NoC, which further constitutes the design philosophy of the proposed Bounded Deflection Adaptive Routing (BDAR) algorithm. Our routing algorithm is deadlock-live lock free and efficiently reacts to link congestions. Experimental results based on simulations show that our routing algorithm performs significantly better than some existing static and dynamic routing in terms of link utilization, average and maximum end-to-end latency.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124091066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4